_primary.vhd

来自「FPGA-CPLD_DesignTool,事例程序1-2」· VHDL 代码 · 共 13 行

library verilog;
use verilog.vl_types.all;
entity alu is
    port(
        clk             : in     vl_logic;
        a               : in     vl_logic_vector(7 downto 0);
        b               : in     vl_logic_vector(7 downto 0);
        opcode          : in     vl_logic_vector(2 downto 0);
        outp_a          : out    vl_logic_vector(7 downto 0);
        outp_s          : out    vl_logic_vector(7 downto 0)
    );
end alu;