dpram_core_demo.npl

来自「FPGA-CPLD_DesignTool,事例程序1-2」· NPL 代码 · 共 26 行

JDF F
// Created by Project Navigator ver 1.0
PROJECT DPRAM_core_Demo
DESIGN dpram_core_demo Normal
DEVFAM virtex2p
DEVFAMTIME 0
DEVICE xc2vp50
DEVICETIME 0
DEVPKG ff1152
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 1036575498
STIMULUS test_fixture.tf Normal
MODULE top.v
MODSTYLE top Normal
MODULE dpram_core.xco
MODSTYLE dpram_core Normal
DEPASSOC top UCF_Demo.ucf SYSTEM
[STATUS-ALL]
top.ncdFile=WARNINGS,1036575631
top.ngcFile=WARNINGS,1036575631
[STRATEGY-LIST]
Normal=True