top.twr

来自「FPGA-CPLD_DesignTool,事例程序1-2」· TWR 代码 · 共 64 行

--------------------------------------------------------------------------------
Release 5.1i - Trace F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

J:/eda/Xilinx/bin/nt/trce.exe -quiet -e 3 -l 3 -xml top top.ncd -o top.twr
top.pcf

Design file:              top.ncd
Physical constraint file: top.pcf
Device,speed:             xc2vp50,-6 (ADVANCED 1.66 2002-07-03)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

WARNING:Timing:2666 - Constraint ignored: TS_P2P = MAXDELAY FROM TIMEGRP "PADS"
   TO TIMEGRP "PADS" 10 nS  ; 


================================================================================
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 10 nS  ; 

 0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clka = PERIOD TIMEGRP "clka"  20 nS   HIGH 50.000000 % ;

 0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_clkb = PERIOD TIMEGRP "clkb"  20 nS   HIGH 50.000000 % ;

 0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.


Timing summary:
---------------

Timing errors: 0  Score: 0

Constraints cover 0 paths, 0 nets, and 42 connections (53.8% coverage)

Design statistics:
No global statistics to report.

Analysis completed Wed Nov 06 17:39:26 2002
--------------------------------------------------------------------------------