top.par

FPGA-CPLD_DesignTool,事例程序1-2

Release 5.1i - Par F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


    ::  Wed Nov 06 17:38:47 2002


J:/eda/Xilinx/bin/nt/par.exe -w -ol 2 -t 1 top_map.ncd top.ncd top.pcf 


Constraints file: top.pcf

Loading device database for application par from file "top_map.ncd".
   "top" is an NCD, version 2.37, device xc2vp50, package ff1152, speed -6
Loading device for application par from file '2vp50.nph' in environment
J:/eda/Xilinx.
Device speed data version:  ADVANCED 1.66 2002-07-03.


Device utilization summary:

   Number of External IOBs            76 out of 692    10%
      Number of LOCed External IOBs    0 out of 76      0%

   Number of RAMB16s                   1 out of 232     1%

   Number of BUFGMUXs                  2 out of 16     12%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)

Starting initial Timing Analysis.  REAL time: 5 secs 
WARNING:Timing:2666 - Constraint ignored: TS_P2P = MAXDELAY FROM TIMEGRP "PADS"
   TO TIMEGRP "PADS" 10 nS  ; 

Finished initial Timing Analysis.  REAL time: 8 secs 


Phase 1.1
Phase 1.1 (Checksum:98976c) REAL time: 8 secs 

Phase 3.23
.....
Phase 3.23 (Checksum:1c9c37d) REAL time: 9 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 9 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 9 secs 

Phase 6.8
.
Phase 6.8 (Checksum:ab1dc7) REAL time: 18 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 18 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 18 secs 

Phase 9.24
Phase 9.24 (Checksum:55d4a77) REAL time: 18 secs 

Writing design to file top.ncd.

Total REAL time to placer completion: 18 secs 
Total CPU time to placer completion: 15 secs 


Starting Router          REAL time: 19 secs 

Phase 1: 100 unrouted;       REAL time: 20 secs 

Phase 2: 74 unrouted;       REAL time: 27 secs 

Phase 3: 20 unrouted; (~0)      REAL time: 27 secs 

Phase 4: 20 unrouted; (~0)      REAL time: 27 secs 

Phase 5: 20 unrouted; (~0)      REAL time: 27 secs 

Phase 6: 0 unrouted; (~0)      REAL time: 28 secs 

Finished Router          REAL time: 28 secs 

Total REAL time to router completion: 28 secs 
Total CPU time to router completion: 24 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|        clkb_BUFGP          |  Global  |    1   |  0.000     |  0.579      |
+----------------------------+----------+--------+------------+-------------+
|        clka_BUFGP          |  Global  |    1   |  0.000     |  0.579      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The Score for this design is: 292


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        2.349 ns
   The Maximum Pin Delay is:                               3.317 ns
   The Average Connection Delay on the 10 Worst Nets is:   2.890 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          26          13          54           7           0           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO  |            |            |      
  TIMEGRP "PADS" 10 nS                      |            |            |      
--------------------------------------------------------------------------------
  TS_clka = PERIOD TIMEGRP "clka"  20 nS    |            |            |      
  HIGH 50.000000 %                          |            |            |      
--------------------------------------------------------------------------------
  TS_clkb = PERIOD TIMEGRP "clkb"  20 nS    |            |            |      
  HIGH 50.000000 %                          |            |            |      
--------------------------------------------------------------------------------


All constraints were met.

All signals are completely routed.

Total REAL time to par completion: 29 secs 
Total CPU time to par completion: 25 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file top.ncd.


PAR done.