dpram_core.asy

来自「FPGA-CPLD_DesignTool,事例程序1-2」· ASY 代码 · 共 48 行

Version 4
SymbolType BLOCK



RECTANGLE Normal 32 0 256 496
PIN 0 48  LEFT 36
PINATTR PinName ADDRA[3:0]
PINATTR Polarity IN
LINE Wide 0 48 32 48
PIN 0 80  LEFT 36
PINATTR PinName DINA[15:0]
PINATTR Polarity IN
LINE Wide 0 80 32 80
PIN 0 112  LEFT 36
PINATTR PinName WEA
PINATTR Polarity IN
LINE Normal 0 112 32 112
PIN 0 240  LEFT 36
PINATTR PinName CLKA
PINATTR Polarity IN
LINE Normal 0 240 32 240
PIN 0 272  LEFT 36
PINATTR PinName ADDRB[3:0]
PINATTR Polarity IN
LINE Wide 0 272 32 272
PIN 0 304  LEFT 36
PINATTR PinName DINB[15:0]
PINATTR Polarity IN
LINE Wide 0 304 32 304
PIN 0 336  LEFT 36
PINATTR PinName WEB
PINATTR Polarity IN
LINE Normal 0 336 32 336
PIN 0 464  LEFT 36
PINATTR PinName CLKB
PINATTR Polarity IN
LINE Normal 0 464 32 464
PIN 288 48  RIGHT 36
PINATTR PinName DOUTA[15:0]
PINATTR Polarity OUT
LINE Wide 256 48 288 48
PIN 288 272  RIGHT 36
PINATTR PinName DOUTB[15:0]
PINATTR Polarity OUT
LINE Wide 256 272 288 272
LINE Wide 256 272 288 272