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Release 5.1i - Map F.23Xilinx Mapping Report File for Design 'top'Design Information------------------Command Line : J:/eda/Xilinx/bin/nt/map.exe -quiet -p xc2vp50-ff1152-6 -cm
area -pr b -k 4 -c 100 -tx off -o top_map.ncd top.ngd top.pcf Target Device : x2vp50Target Package : ff1152Target Speed : -6Mapper Version : virtex2p -- $Revision: 1.4 $Mapped Date : Wed Nov 06 17:38:36 2002Design Summary-------------- Number of errors: 0 Number of warnings: 0 Number of Slices containing unrelated logic: 0 out of 0 0% Number of bonded IOBs: 76 out of 692 10% Number of Block RAMs: 1 out of 232 1% Number of GCLKs: 2 out of 16 12%Total equivalent gate count for design: 65,542Additional JTAG gate count for IOBs: 3,648Peak Memory Usage: 155 MBTable of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFGP symbol "clka_BUFGP" (output signal=clka_BUFGP), BUFGP symbol "clkb_BUFGP" (output signal=clkb_BUFGP)INFO:LIT:95 - All of the external outputs in this design are using slew rate
limited output drivers. The delay on speed critical outputs can be
dramatically reduced by designating them as fast outputs in the schematic.Section 4 - Removed Logic Summary--------------------------------- 2 block(s) optimized awaySection 5 - Removed Logic-------------------------Optimized Block(s):TYPE BLOCKGND dpram_inst/GNDVCC dpram_inst/VCCSection 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| addra<0> | IOB | INPUT | LVCMOS25 | | | | | || addra<1> | IOB | INPUT | LVCMOS25 | | | | | || addra<2> | IOB | INPUT | LVCMOS25 | | | | | || addra<3> | IOB | INPUT | LVCMOS25 | | | | | || addrb<0> | IOB | INPUT | LVCMOS25 | | | | | || addrb<1> | IOB | INPUT | LVCMOS25 | | | | | || addrb<2> | IOB | INPUT | LVCMOS25 | | | | | || addrb<3> | IOB | INPUT | LVCMOS25 | | | | | || clka | IOB | INPUT | LVCMOS25 | | | | | || clkb | IOB | INPUT | LVCMOS25 | | | | | || dina<0> | IOB | INPUT | LVCMOS25 | | | | | || dina<1> | IOB | INPUT | LVCMOS25 | | | | | || dina<2> | IOB | INPUT | LVCMOS25 | | | | | || dina<3> | IOB | INPUT | LVCMOS25 | | | | | || dina<4> | IOB | INPUT | LVCMOS25 | | | | | || dina<5> | IOB | INPUT | LVCMOS25 | | | | | || dina<6> | IOB | INPUT | LVCMOS25 | | | | | || dina<7> | IOB | INPUT | LVCMOS25 | | | | | || dina<8> | IOB | INPUT | LVCMOS25 | | | | | || dina<9> | IOB | INPUT | LVCMOS25 | | | | | || dina<10> | IOB | INPUT | LVCMOS25 | | | | | || dina<11> | IOB | INPUT | LVCMOS25 | | | | | || dina<12> | IOB | INPUT | LVCMOS25 | | | | | || dina<13> | IOB | INPUT | LVCMOS25 | | | | | || dina<14> | IOB | INPUT | LVCMOS25 | | | | | || dina<15> | IOB | INPUT | LVCMOS25 | | | | | || dinb<0> | IOB | INPUT | LVCMOS25 | | | | | || dinb<1> | IOB | INPUT | LVCMOS25 | | | | | || dinb<2> | IOB | INPUT | LVCMOS25 | | | | | || dinb<3> | IOB | INPUT | LVCMOS25 | | | | | || dinb<4> | IOB | INPUT | LVCMOS25 | | | | | || dinb<5> | IOB | INPUT | LVCMOS25 | | | | | || dinb<6> | IOB | INPUT | LVCMOS25 | | | | | || dinb<7> | IOB | INPUT | LVCMOS25 | | | | | || dinb<8> | IOB | INPUT | LVCMOS25 | | | | | || dinb<9> | IOB | INPUT | LVCMOS25 | | | | | || dinb<10> | IOB | INPUT | LVCMOS25 | | | | | || dinb<11> | IOB | INPUT | LVCMOS25 | | | | | || dinb<12> | IOB | INPUT | LVCMOS25 | | | | | || dinb<13> | IOB | INPUT | LVCMOS25 | | | | | || dinb<14> | IOB | INPUT | LVCMOS25 | | | | | || dinb<15> | IOB | INPUT | LVCMOS25 | | | | | || douta<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || douta<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || doutb<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || wea | IOB | INPUT | LVCMOS25 | | | | | || web | IOB | INPUT | LVCMOS25 | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------No area groups were found in this design.Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.⌨️ 快捷键说明
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