test_wave.tfw

FPGA-CPLD_DesignTool,事例程序1-2

// J:\PROJECTS\ISE\COREGENDEMO\DPRAM_CORE_DEMO
// Verilog Test fixture created by
// HDL Bencher 5.1i
// Wed Nov 06 18:09:22 2002
// 
// Notes:
// 1) This test fixture has been automatically generated from
//   your Test Bench Waveform
// 2) To use this as a user modifiable test fixture do the following:
//   - Save it as a file with a .tf extension (i.e. File->Save As...)
//   - Add it to your project as a testbench source (i.e. Project->Add Source...)
// 

`timescale 1ns/1ns

module testbench;
	reg [3:0] addra;
	reg [3:0] addrb;
	reg clka;
	reg clkb;
	reg [15:0] dina;
	reg [15:0] dinb;
	wire [15:0] douta;
	wire [15:0] doutb;
	reg wea;
	reg web;

	top UUT (
		.addra(addra),
		.addrb(addrb),
		.clka(clka),
		.clkb(clkb),
		.dina(dina),
		.dinb(dinb),
		.douta(douta),
		.doutb(doutb),
		.wea(wea),
		.web(web)
	);

	integer TX_FILE;
	integer TX_ERROR;

always
begin 			//clock process
	clkb = 1'b0;
	#10
	clkb = 1'b1;
	#10
	#40
	clkb = 1'b0;
	#40
	clkb = 1'b0;
end

initial
begin
	TX_ERROR=0;
	TX_FILE=$fopen("results.txt");

	// --------------------
	addra = 4'b0001; //1
	addrb = 4'b0000; //0
	clka = 1'b0;
	dina = 16'b0000000000000000; //0
	dinb = 16'b0000000000000000; //0
	wea = 1'b0;
	web = 1'b0;
	// --------------------
	#100 // Time=100 ns
	addra = 4'b1111; //F
	addrb = 4'b0001; //1
	// --------------------
	#100 // Time=200 ns
	addra = 4'b1110; //E
	addrb = 4'b0000; //0
	// --------------------
	#100 // Time=300 ns
	addra = 4'b1101; //D
	addrb = 4'b0001; //1
	// --------------------
	#100 // Time=400 ns
	addra = 4'b1100; //C
	addrb = 4'b0000; //0
	// --------------------
	#100 // Time=500 ns
	addra = 4'b1011; //B
	addrb = 4'b0001; //1
	// --------------------
	#100 // Time=600 ns
	addra = 4'b1010; //A
	addrb = 4'b0000; //0
	// --------------------
	#100 // Time=700 ns
	addra = 4'b1001; //9
	addrb = 4'b0001; //1
	// --------------------
	#100 // Time=800 ns
	addra = 4'b1000; //8
	addrb = 4'b0000; //0
	// --------------------
	#100 // Time=900 ns
	addrb = 4'b0001; //1
	// --------------------
	#100 // Time=1000 ns
	addrb = 4'b0000; //0
	// --------------------
	#10 // Time=1010 ns
	// --------------------

	if (TX_ERROR == 0) begin
		$display("No errors or warnings");
		$fdisplay(TX_FILE,"No errors or warnings");
	end else begin
		$display("%d errors found in simulation",TX_ERROR);
		$fdisplay(TX_FILE,"%d errors found in simulation",TX_ERROR);
	end

	$fclose(TX_FILE);
	$stop;

end

task CHECK_douta;
	input [15:0] NEXT_douta;

	#0 begin
		if (NEXT_douta !== douta) begin
			$display("Error at time=%dns douta=%b, expected=%b",
				$time, douta, NEXT_douta);
			$fdisplay(TX_FILE,"Error at time=%dns douta=%b, expected=%b",
				$time, douta, NEXT_douta);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

task CHECK_doutb;
	input [15:0] NEXT_doutb;

	#0 begin
		if (NEXT_doutb !== doutb) begin
			$display("Error at time=%dns doutb=%b, expected=%b",
				$time, doutb, NEXT_doutb);
			$fdisplay(TX_FILE,"Error at time=%dns doutb=%b, expected=%b",
				$time, doutb, NEXT_doutb);
			TX_ERROR = TX_ERROR + 1;
		end
	end
endtask

endmodule