fdq.sym

来自「FPGA-CPLD_DesignTool,事例程序1-2」· SYM 代码 · 共 33 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 11 12 8 34 56
SYMPIN 0 -96 Input "Din"
SYMPIN 0 -32 Input "clk"
SYMPIN 384 -96 Output "Q"
SYMPIN 384 -32 Output "Qo"
RECTANGLE N 64 -128 320 0 
BEGIN DISPLAY 192 -136 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 64 -96 0 -96 
BEGIN DISPLAY 72 -96 PIN "Din" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -32 0 -32 
BEGIN DISPLAY 72 -32 PIN "clk" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
LINE N 320 -96 384 -96 
BEGIN DISPLAY 312 -96 PIN "Q" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
LINE N 320 -32 384 -32 
BEGIN DISPLAY 312 -32 PIN "Qo" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
END SYMBOL