mode7cnt.sym

来自「FPGA-CPLD_DesignTool,事例程序1-2」· SYM 代码 · 共 23 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 11 14 4 12 48
SYMPIN 0 -32 Input "clk"
SYMPIN 384 -32 Output "Q(2:0)"
BEGIN DISPLAY 192 -72 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -32 PIN "clk" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 312 -32 PIN "Q(2:0)" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
LINE N 320 -32 384 -32 
RECTANGLE N 320 -44 384 -20 
LINE N 64 -32 0 -32 
RECTANGLE N 64 -64 320 0 
END SYMBOL