andnor2.sym

来自「FPGA-CPLD_DesignTool,事例程序1-2」· SYM 代码 · 共 37 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2002 11 12 9 13 3
SYMPIN 0 -224 Input "in1"
SYMPIN 0 -160 Input "in2"
SYMPIN 0 -96 Input "in3"
SYMPIN 0 -32 Input "in4"
SYMPIN 384 32 Output "out_t"
BEGIN DISPLAY 192 -264 ATTR "SymbolName"
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -224 PIN "in1" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -160 PIN "in2" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -96 PIN "in3" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
BEGIN DISPLAY 72 -32 PIN "in4" ATTR "PinName"
    FONT 24 "Arial"
END DISPLAY
LINE N 320 32 384 32 
BEGIN DISPLAY 312 32 PIN "out_t" ATTR "PinName"
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
LINE N 64 -224 0 -224 
LINE N 64 -160 0 -160 
LINE N 64 -96 0 -96 
LINE N 64 -32 0 -32 
RECTANGLE N 64 -256 320 64 
END SYMBOL