mode7cnt.stx

FPGA-CPLD_DesignTool,事例程序1-2

Release 5.1i - xst F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "mode7cnt.sprj"
Compiling include file "fdq.vf"
Module <fdq> compiled
Compiling include file "and4or2.vf"
Module <and4or2> compiled
Compiling include file "and5or2.vf"
Module <and5or2> compiled
Compiling include file "mode7cnt.vf"
Module <mode7cnt> compiled
Compiling include file "J:/eda/Xilinx/verilog/src/iSE/unisim_comp.v"
No errors in compilation
Analysis of file <mode7cnt.sprj> succeeded.

CPU : 0.74 / 1.18 s | Elapsed : 1.00 / 1.00 s
 
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Total memory usage is 52080 kilobytes