and5or2.sch

FPGA-CPLD_DesignTool,事例程序1-2

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "virtexe"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL "out_t"
        SIGNAL "XLXN_8"
        SIGNAL "in1"
        SIGNAL "in2"
        SIGNAL "in3"
        SIGNAL "in5"
        SIGNAL "XLXN_9"
        SIGNAL "in4"
        PORT Output "out_t"
        PORT Input "in1"
        PORT Input "in2"
        PORT Input "in3"
        PORT Input "in5"
        PORT Input "in4"
        BEGIN BLOCKDEF "and2"
            TIMESTAMP 2001 2 2 12 25 36
            LINE N 0 -64 64 -64 
            LINE N 0 -128 64 -128 
            LINE N 256 -96 192 -96 
            ARC N 96 -144 192 -48 144 -48 144 -144 
            LINE N 144 -48 64 -48 
            LINE N 64 -144 144 -144 
            LINE N 64 -48 64 -144 
        END BLOCKDEF
        BEGIN BLOCKDEF "or2"
            TIMESTAMP 2001 2 2 12 25 36
            LINE N 0 -64 64 -64 
            LINE N 0 -128 64 -128 
            LINE N 256 -96 192 -96 
            ARC N 28 -224 204 -48 112 -48 192 -96 
            ARC N -40 -152 72 -40 48 -48 48 -144 
            LINE N 112 -144 48 -144 
            ARC N 28 -144 204 32 192 -96 112 -144 
            LINE N 112 -48 48 -48 
        END BLOCKDEF
        BEGIN BLOCKDEF "and3"
            TIMESTAMP 2001 2 2 12 25 36
            LINE N 0 -64 64 -64 
            LINE N 0 -128 64 -128 
            LINE N 0 -192 64 -192 
            LINE N 256 -128 192 -128 
            LINE N 64 -176 144 -176 
            LINE N 144 -80 64 -80 
            ARC N 96 -176 192 -80 144 -80 144 -176 
            LINE N 64 -64 64 -192 
        END BLOCKDEF
        BEGIN BLOCK "XLXI_2" "and2"
            PIN "I0" "in2"
            PIN "I1" "in1"
            PIN "O" "XLXN_9"
        END BLOCK
        BEGIN BLOCK "XLXI_3" "or2"
            PIN "I0" "XLXN_8"
            PIN "I1" "XLXN_9"
            PIN "O" "out_t"
        END BLOCK
        BEGIN BLOCK "XLXI_4" "and3"
            PIN "I0" "in5"
            PIN "I1" "in4"
            PIN "I2" "in3"
            PIN "O" "XLXN_8"
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        BEGIN BRANCH "out_t"
            WIRE 2016 1168 2032 1168
            WIRE 2032 1168 2048 1168
        END BRANCH
        BEGIN BRANCH "XLXN_8"
            WIRE 1728 1248 1744 1248
            WIRE 1744 1200 1760 1200
            WIRE 1744 1200 1744 1248
        END BRANCH
        BEGIN BRANCH "in1"
            WIRE 1424 1056 1456 1056
            WIRE 1456 1056 1472 1056
        END BRANCH
        BEGIN BRANCH "in2"
            WIRE 1424 1120 1456 1120
            WIRE 1456 1120 1472 1120
        END BRANCH
        INSTANCE "XLXI_2" 1472 1184 R0
        INSTANCE "XLXI_3" 1760 1264 R0
        IOMARKER 1424 1056 "in1" R180 28
        IOMARKER 1424 1120 "in2" R180 28
        IOMARKER 2048 1168 "out_t" R0 28
        INSTANCE "XLXI_4" 1472 1376 R0
        BEGIN BRANCH "in3"
            WIRE 1424 1184 1456 1184
            WIRE 1456 1184 1472 1184
        END BRANCH
        BEGIN BRANCH "in5"
            WIRE 1424 1312 1456 1312
            WIRE 1456 1312 1472 1312
        END BRANCH
        IOMARKER 1424 1184 "in3" R180 28
        IOMARKER 1424 1312 "in5" R180 28
        BEGIN BRANCH "XLXN_9"
            WIRE 1728 1088 1744 1088
            WIRE 1744 1088 1744 1136
            WIRE 1744 1136 1760 1136
        END BRANCH
        BEGIN BRANCH "in4"
            WIRE 1408 1248 1472 1248
        END BRANCH
        IOMARKER 1408 1248 "in4" R180 28
    END SHEET
END SCHEMATIC