and4or2.sch

FPGA-CPLD_DesignTool,事例程序1-2

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "virtexe"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL "out_t"
        SIGNAL "in1"
        SIGNAL "in2"
        SIGNAL "in3"
        SIGNAL "in4"
        SIGNAL "XLXN_7"
        SIGNAL "XLXN_8"
        PORT Output "out_t"
        PORT Input "in1"
        PORT Input "in2"
        PORT Input "in3"
        PORT Input "in4"
        BEGIN BLOCKDEF "and2"
            TIMESTAMP 2001 2 2 12 25 36
            LINE N 0 -64 64 -64 
            LINE N 0 -128 64 -128 
            LINE N 256 -96 192 -96 
            ARC N 96 -144 192 -48 144 -48 144 -144 
            LINE N 144 -48 64 -48 
            LINE N 64 -144 144 -144 
            LINE N 64 -48 64 -144 
        END BLOCKDEF
        BEGIN BLOCKDEF "or2"
            TIMESTAMP 2001 2 2 12 25 36
            LINE N 0 -64 64 -64 
            LINE N 0 -128 64 -128 
            LINE N 256 -96 192 -96 
            ARC N 28 -224 204 -48 112 -48 192 -96 
            ARC N -40 -152 72 -40 48 -48 48 -144 
            LINE N 112 -144 48 -144 
            ARC N 28 -144 204 32 192 -96 112 -144 
            LINE N 112 -48 48 -48 
        END BLOCKDEF
        BEGIN BLOCK "XLXI_1" "and2"
            PIN "I0" "in2"
            PIN "I1" "in1"
            PIN "O" "XLXN_7"
        END BLOCK
        BEGIN BLOCK "XLXI_2" "and2"
            PIN "I0" "in4"
            PIN "I1" "in3"
            PIN "O" "XLXN_8"
        END BLOCK
        BEGIN BLOCK "XLXI_3" "or2"
            PIN "I0" "XLXN_8"
            PIN "I1" "XLXN_7"
            PIN "O" "out_t"
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        BEGIN BRANCH "out_t"
            WIRE 1584 928 1600 928
            WIRE 1600 928 1616 928
        END BRANCH
        BEGIN BRANCH "XLXN_7"
            WIRE 1296 848 1312 848
            WIRE 1312 848 1312 896
            WIRE 1312 896 1328 896
        END BRANCH
        BEGIN BRANCH "XLXN_8"
            WIRE 1296 1008 1312 1008
            WIRE 1312 960 1312 1008
            WIRE 1312 960 1328 960
        END BRANCH
        BEGIN BRANCH "in1"
            WIRE 992 816 1024 816
            WIRE 1024 816 1040 816
        END BRANCH
        BEGIN BRANCH "in2"
            WIRE 992 880 1024 880
            WIRE 1024 880 1040 880
        END BRANCH
        BEGIN BRANCH "in3"
            WIRE 992 976 1024 976
            WIRE 1024 976 1040 976
        END BRANCH
        BEGIN BRANCH "in4"
            WIRE 992 1040 1024 1040
            WIRE 1024 1040 1040 1040
        END BRANCH
        INSTANCE "XLXI_2" 1040 1104 R0
        INSTANCE "XLXI_1" 1040 944 R0
        IOMARKER 992 816 "in1" R180 28
        IOMARKER 992 880 "in2" R180 28
        IOMARKER 992 976 "in3" R180 28
        IOMARKER 992 1040 "in4" R180 28
        INSTANCE "XLXI_3" 1328 1024 R0
        IOMARKER 1616 928 "out_t" R0 28
    END SHEET
END SCHEMATIC