fdq.sch

FPGA-CPLD_DesignTool,事例程序1-2

VERSION 6
BEGIN SCHEMATIC
    BEGIN ATTR DeviceFamilyName "virtexe"
        DELETE all:0
        EDITNAME all:0
        EDITTRAIT all:0
    END ATTR
    BEGIN NETLIST
        SIGNAL "Din"
        SIGNAL "clk"
        SIGNAL "XLXN_3"
        SIGNAL "Q"
        SIGNAL "Qo"
        PORT Input "Din"
        PORT Input "clk"
        PORT Output "Q"
        PORT Output "Qo"
        BEGIN BLOCKDEF "fd"
            TIMESTAMP 2001 5 4 16 43 47
            RECTANGLE N 64 -320 320 -64 
            LINE N 0 -128 64 -128 
            LINE N 0 -256 64 -256 
            LINE N 384 -256 320 -256 
            LINE N 80 -128 64 -144 
            LINE N 64 -112 80 -128 
        END BLOCKDEF
        BEGIN BLOCKDEF "inv"
            TIMESTAMP 2001 2 2 12 25 36
            LINE N 0 -32 64 -32 
            LINE N 224 -32 160 -32 
            LINE N 64 -64 128 -32 
            LINE N 128 -32 64 0 
            LINE N 64 0 64 -64 
            CIRCLE N 128 -48 160 -16 
        END BLOCKDEF
        BEGIN BLOCK "XLXI_1" "fd"
            PIN "C" "clk"
            PIN "D" "Din"
            PIN "Q" "Q"
        END BLOCK
        BEGIN BLOCK "XLXI_2" "inv"
            PIN "I" "Q"
            PIN "O" "Qo"
        END BLOCK
    END NETLIST
    BEGIN SHEET 1 3520 2720
        INSTANCE "XLXI_1" 1216 1136 R0
        BEGIN BRANCH "Din"
            WIRE 1120 880 1216 880
        END BRANCH
        BEGIN BRANCH "clk"
            WIRE 1120 1008 1216 1008
        END BRANCH
        INSTANCE "XLXI_2" 1696 1056 R0
        BEGIN BRANCH "Q"
            WIRE 1600 880 1632 880
            WIRE 1632 880 1632 1024
            WIRE 1632 1024 1696 1024
            WIRE 1632 880 2000 880
        END BRANCH
        BEGIN BRANCH "Qo"
            WIRE 1920 1024 2000 1024
        END BRANCH
        IOMARKER 1120 880 "Din" R180 28
        IOMARKER 1120 1008 "clk" R180 28
        IOMARKER 2000 880 "Q" R0 28
        IOMARKER 2000 1024 "Qo" R0 28
    END SHEET
END SCHEMATIC