📄 p9054_lib.c
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// verification that bits 0-3 are zero (quadword aligned)
pList = (DMA_LIST *) ((DWORD) hDma->dmaList.pUserAddr + dwAlignShift);
for (dwPageNumber=0; dwPageNumber<hDma->dma.dwPages; dwPageNumber++)
{
pList[dwPageNumber].dwPADR = (DWORD) hDma->dma.Page[dwPageNumber].pPhysicalAddr;
pList[dwPageNumber].dwLADR = dwLocalAddr + (fAutoinc ? dwMemoryCopied : 0);
pList[dwPageNumber].dwSIZ = hDma->dma.Page[dwPageNumber].dwBytes;
pList[dwPageNumber].dwDPR =
((DWORD) hDma->dmaList.Page[0].pPhysicalAddr + dwAlignShift + sizeof(DMA_LIST)*(dwPageNumber+1))
| BIT0 | (fIsRead ? BIT3 : 0);
dwMemoryCopied += hDma->dma.Page[dwPageNumber].dwBytes;
}
pList[dwPageNumber - 1].dwDPR |= BIT1; // mark end of chain
dwDMAMODE = (fAutoinc ? 0 : BIT11)
| BIT6
| BIT9 // chain transfer
| (mode==P9054_MODE_BYTE ? 0 : mode==P9054_MODE_WORD ? BIT0 : (BIT1 | BIT0));
dwDMADPR = ((DWORD)hDma->dmaList.Page[0].pPhysicalAddr + dwAlignShift) | BIT0;
// starting the dma
P9054_WriteReg (hPlx, P9054_DMAMODE + dwChannelShift, dwDMAMODE);
P9054_WriteReg (hPlx, P9054_DMADPR + dwChannelShift, dwDMADPR);
}
//*********************LTB
P9054_DMAStart (hPlx, hDma, 1);
P9054_DMAClose (hPlx, hDma);
//*********************LTB
return hDma;
Exit:
if (hDma!=NULL)
P9054_DMAClose(hPlx,hDma);
return NULL;
}
P9054_DMA_HANDLE P9054_DMA_Large_Buffer (P9054_HANDLE hPlx, DWORD dwLocalAddr, PVOID buf,
DWORD dwBytes, BOOL fIsRead, P9054_MODE mode, P9054_DMA_CHANNEL dmaChannel)
{
DWORD dwDMAMODE, dwDMADPR, dwDMALADR;
DWORD dwChannelShift = (dmaChannel==P9054_DMA_CHANNEL_0) ? 0 : P9054_DMA_CHANNEL_SHIFT;
BOOL fAutoinc = TRUE;
P9054_DMA_HANDLE hDma;
DWORD dwStatus;
//************
//LTB: added codes for Large Buffer Mode
DWORD dwPagesNeeded = dwBytes / 4096 + 2;
// WD_DMA structure already has space for WD_DMA_PAGES
// number of entries
hDma = (P9054_DMA_HANDLE) malloc (sizeof(P9054_DMA_STRUCT));
if (hDma==NULL)
{
sprintf(P9054_ErrorString, "Failed allocating memory for dma handle!\n");
goto Exit;
}
BZERO (*hDma);
hDma->dmaChannel = dmaChannel;
hDma->dma.dwBytes = dwBytes;
hDma->dma.pUserAddr = buf;
hDma->dma.dwOptions = DMA_LARGE_BUFFER;
hDma->dma.dwPages = dwPagesNeeded;
dwStatus = WD_DMALock(hPlx->hWD, &hDma->dma);
if (dwStatus)
{
sprintf(P9054_ErrorString, "Failed locking the buffer. status 0x%x - %s\n",
dwStatus, Stat2Str(dwStatus));
goto Exit;
}
if (hDma->dma.dwPages==1)
{
//dma of one page ==> direct dma
dwDMAMODE =
(fAutoinc ? 0 : BIT11)
| BIT6
| (mode==P9054_MODE_BYTE ? 0 : mode==P9054_MODE_WORD ? BIT0 : (BIT1 | BIT0));
dwDMADPR = BIT0 | (fIsRead ? BIT3 : 0);
dwDMALADR = dwLocalAddr;
P9054_WriteReg (hPlx, P9054_DMAMODE + dwChannelShift, dwDMAMODE);
P9054_WriteReg (hPlx, P9054_DMAPADR + dwChannelShift, (DWORD) hDma->dma.Page[0].pPhysicalAddr);
P9054_WriteReg (hPlx, P9054_DMALADR + dwChannelShift, dwDMALADR);
P9054_WriteReg (hPlx, P9054_DMASIZ + dwChannelShift, hDma->dma.Page[0].dwBytes);
P9054_WriteReg (hPlx, P9054_DMADPR + dwChannelShift, dwDMADPR);
}
else
{
DWORD dwAlignShift, dwPageNumber, dwMemoryCopied;
typedef struct {
DWORD dwPADR;
DWORD dwLADR;
DWORD dwSIZ;
DWORD dwDPR;
} DMA_LIST;
DMA_LIST *pList;
// dma of more then one page ==> chain dma
// includes extra 0x10 bytes for quadword alignment
hDma->dmaList.dwBytes = hDma->dma.dwPages * sizeof(DMA_LIST) + 0x10;
hDma->dmaList.pUserAddr = NULL;
hDma->dmaList.dwOptions = DMA_KERNEL_BUFFER_ALLOC;
dwStatus = WD_DMALock(hPlx->hWD, &hDma->dmaList);
if (dwStatus)
{
sprintf(P9054_ErrorString, "Failed allocating the chain buffer. status 0x%x - %s\n",
dwStatus, Stat2Str(dwStatus));
goto Exit;
}
//setting chain of dma pages in the memory
dwMemoryCopied = 0;
dwAlignShift = 0x10 - (DWORD) hDma->dmaList.pUserAddr & 0xf;
// verification that bits 0-3 are zero (quadword aligned)
pList = (DMA_LIST *) ((DWORD) hDma->dmaList.pUserAddr + dwAlignShift);
for (dwPageNumber=0; dwPageNumber<hDma->dma.dwPages; dwPageNumber++)
{
pList[dwPageNumber].dwPADR = (DWORD) hDma->dma.Page[dwPageNumber].pPhysicalAddr;
pList[dwPageNumber].dwLADR = dwLocalAddr + (fAutoinc ? dwMemoryCopied : 0);
pList[dwPageNumber].dwSIZ = hDma->dma.Page[dwPageNumber].dwBytes;
pList[dwPageNumber].dwDPR =
((DWORD) hDma->dmaList.Page[0].pPhysicalAddr + dwAlignShift + sizeof(DMA_LIST)*(dwPageNumber+1))
| BIT0 | (fIsRead ? BIT3 : 0);
dwMemoryCopied += hDma->dma.Page[dwPageNumber].dwBytes;
}
pList[dwPageNumber - 1].dwDPR |= BIT1; // mark end of chain
dwDMAMODE = (fAutoinc ? 0 : BIT11) //LTB: fAutoinc=TRUE, So "0" is selected, indicates the Local Address is incremented.
| BIT6 //LTB: enables TA#/READY# input
| BIT9 // chain transfer //LTB: Scatter/gather DMA mode
| (mode==P9054_MODE_BYTE ? 0 : mode==P9054_MODE_WORD ? BIT0 : (BIT1 | BIT0));
dwDMADPR = ((DWORD)hDma->dmaList.Page[0].pPhysicalAddr + dwAlignShift) | BIT0;
// starting the dma
P9054_WriteReg (hPlx, P9054_DMAMODE + dwChannelShift, dwDMAMODE);
P9054_WriteReg (hPlx, P9054_DMADPR + dwChannelShift, dwDMADPR);
}
return hDma;
Exit:
if (hDma!=NULL)
P9054_DMAClose(hPlx,hDma);
return NULL;
}
void P9054_DMAClose (P9054_HANDLE hPlx, P9054_DMA_HANDLE hDma)
{
if (hDma->dma.hDma)
WD_DMAUnlock(hPlx->hWD, &hDma->dma);
if (hDma->dmaList.hDma)
WD_DMAUnlock(hPlx->hWD, &hDma->dmaList);
free (hDma);
}
BOOL P9054_DMAIsDone (P9054_HANDLE hPlx, P9054_DMA_HANDLE hDma)
{
return (P9054_ReadByte(hPlx, P9054_ADDR_REG, P9054_DMACSR +
hDma->dmaChannel) & BIT4) == BIT4;
}
void P9054_DMAStart (P9054_HANDLE hPlx, P9054_DMA_HANDLE hDma, BOOL fBlocking)
{
//*****************LTB: replaced with no hDma
/*
P9054_WriteByte (hPlx, P9054_ADDR_REG, P9054_DMACSR + hDma->dmaChannel,
BIT0 | BIT1);
*/
P9054_WriteByte (hPlx, P9054_ADDR_REG, P9054_DMACSR,
BIT0 | BIT1);
//*****************LTB: end
//Busy wait for plx to finish transfer
if (fBlocking)
while (!P9054_DMAIsDone(hPlx, hDma))
;
}
BOOL P9054_DMAReadWriteBlock (P9054_HANDLE hPlx, DWORD dwLocalAddr, PVOID buf,
DWORD dwBytes, BOOL fIsRead, P9054_MODE mode, P9054_DMA_CHANNEL dmaChannel)
{
P9054_DMA_HANDLE hDma;
if (dwBytes==0)
return TRUE;
hDma = P9054_DMAOpen(hPlx, dwLocalAddr, buf, dwBytes, fIsRead, mode, dmaChannel);
if (!hDma)
return FALSE;
P9054_DMAStart(hPlx, hDma, TRUE);
P9054_DMAClose(hPlx, hDma);
return TRUE;
}
BOOL P9054_EEPROMValid(P9054_HANDLE hPlx)
{
return (P9054_ReadReg(hPlx, P9054_CNTRL) & BIT28)==BIT28;
}
BOOL P9054_EEPROMReadWord(P9054_HANDLE hPlx, DWORD dwOffset, PWORD pwData)
{
DWORD dwData;
DWORD dwAddr;
if (dwOffset % 2)
{
sprintf(P9054_ErrorString, "The offset is not even\n");
return FALSE;
}
dwAddr = dwOffset - (dwOffset % 4);
if (!P9054_EEPROMReadDWord(hPlx, dwAddr, &dwData))
return FALSE;
*pwData = (WORD) (dwData >> ((dwOffset % 4)*8));
return TRUE;
}
BOOL P9054_EEPROMWriteWord(P9054_HANDLE hPlx, DWORD dwOffset, WORD wData)
{
DWORD dwData;
DWORD dwAddr;
dwAddr = dwOffset - (dwOffset % 4);
if (!P9054_EEPROMReadDWord(hPlx, dwAddr, &dwData))
return FALSE;
switch (dwOffset % 4)
{
case 0:
dwData = (dwData & 0xffff0000) | wData;
break;
case 2:
dwData = (dwData & 0x0000ffff) | (wData << 16);
break;
default:
sprintf(P9054_ErrorString, "The offset is not even\n");
return FALSE;
}
return P9054_EEPROMWriteDWord(hPlx, dwAddr, dwData);
}
void P9054_Sleep(P9054_HANDLE hPlx, DWORD dwMicroSeconds)
{
WD_SLEEP sleep;
BZERO (sleep);
sleep.dwMicroSeconds = dwMicroSeconds;
WD_Sleep( hPlx->hWD, &sleep);
}
BYTE P9054_EEPROMEnable(P9054_HANDLE hPlx, WORD addr)
{
BYTE old_val;
old_val = P9054_ReadByte(hPlx, P9054_ADDR_REG, P9054_PROT_AREA);
addr /= 4;
addr &= 0x7f;
P9054_WriteByte(hPlx, P9054_ADDR_REG, P9054_PROT_AREA, (BYTE)addr);
P9054_Sleep(hPlx, 10000);
return (BYTE)(old_val * 4); //expand from dwords to bytes
}
void P9054_EEPROMDataReadWrite(P9054_HANDLE hPlx, BOOL fIsRead, PDWORD pdwData)
{
WD_PCI_CONFIG_DUMP pciCnf;
BZERO (pciCnf);
pciCnf.pciSlot = hPlx->pciSlot;
pciCnf.pBuffer = pdwData;
pciCnf.dwOffset = P9054_VPD_DATA;
pciCnf.dwBytes = 4;
pciCnf.fIsRead = fIsRead;
WD_PciConfigDump(hPlx->hWD,&pciCnf);
}
void P9054_EEPROMAddrReadWrite(P9054_HANDLE hPlx, BOOL fIsRead, PWORD pwAddr)
{
WD_PCI_CONFIG_DUMP pciCnf;
BZERO (pciCnf);
pciCnf.pciSlot = hPlx->pciSlot;
pciCnf.pBuffer = pwAddr;
pciCnf.dwOffset = P9054_VPD_ADDR;
pciCnf.dwBytes = 2;
pciCnf.fIsRead = fIsRead;
WD_PciConfigDump(hPlx->hWD,&pciCnf);
}
BOOL P9054_EEPROMReadDWord(P9054_HANDLE hPlx, DWORD dwOffset, PDWORD pdwData)
{
WORD wVal;
WORD wAddr;
int i;
if (dwOffset % 4)
{
sprintf(P9054_ErrorString, "The offset is not a multiple of 4\n");
return FALSE;
}
wAddr = (((WORD)dwOffset) & (~BIT15)) ;
for (i=0; i<10; i++)
{
P9054_EEPROMAddrReadWrite(hPlx, FALSE, &wAddr);
P9054_Sleep(hPlx, 10000);
P9054_EEPROMAddrReadWrite(hPlx, TRUE, &wVal);
if (wVal & BIT15)
break;
}
if (i==10)
{
sprintf(P9054_ErrorString, "Acknowledge to EEPROM read was not received\n");
return FALSE;
}
P9054_EEPROMDataReadWrite(hPlx, TRUE, pdwData);
return TRUE;
}
BOOL P9054_EEPROMWriteDWord(P9054_HANDLE hPlx, DWORD dwOffset, DWORD dwData)
{
DWORD dwReadback;
WORD wAddr;
WORD wVal;
int i;
BOOL fRet;
BOOL fReadOk = FALSE;
BYTE bEnableOffset;
if (dwOffset % 4)
{
sprintf(P9054_ErrorString, "The offset is not a multiple of 4\n");
return FALSE;
}
wAddr = (WORD)dwOffset;
bEnableOffset = P9054_EEPROMEnable(hPlx, wAddr);
wAddr = (WORD)(wAddr | BIT15);
for (i=0; i<10; i++)
{
P9054_EEPROMDataReadWrite(hPlx, FALSE, &dwData);
P9054_EEPROMAddrReadWrite(hPlx, FALSE, &wAddr);
P9054_Sleep(hPlx, 10000);
P9054_EEPROMAddrReadWrite(hPlx, TRUE, &wVal);
if ((wVal & BIT15) == 0)
break;
}
fReadOk = P9054_EEPROMReadDWord(hPlx, dwOffset, &dwReadback);
if (fReadOk && dwReadback==dwData)
fRet = TRUE;
else
{
fRet = FALSE;
if (fReadOk)
sprintf(P9054_ErrorString, "Write 0x%08x, Read 0x%08x\n",dwData, dwReadback);
else
sprintf(P9054_ErrorString, "Error reading EEPROM\n");
}
P9054_EEPROMEnable(hPlx, bEnableOffset);
return fRet;
}
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