fpga测频.txt

基于Verilog HDL语言的FPGA源程序

module frequency(RD,WR,ad,lk,hk,CS,A,clk,freq,ALE,aout,int,clear);
    input freq,clear,clk,RD,WR,ALE;
    input [15:13] A;
    input [4:1] hk;
    inout [7:0] ad;
    output [4:1] lk;
    output [3:0] CS;
    output [7:0] aout;
	 output int;
    reg [7:0] aout;
    reg [4:1] lk;  
    reg [3:0] CS;
	 reg en,int;
	 reg [1:0] flag;
	 reg [21:0] i;
	 reg [23:0] j;
	 reg [7:0] adbuff;

   initial
	 begin
    i<=0;		  //标准时钟计数器
	 j<=0;		  //待测量计数器
	 int<=0;		  //测量结束标志
	 end

  always@(posedge freq)
	 begin
	   if((!int)&&flag[1]&&flag[0]&&(!clear))		 //测量启动
		 	j<=j+1;
      if(flag[1]&&(!flag[0])&&clear)			    //数据传输结束后清零计数器
		   j<=0;
   end


 always@(posedge clk)
	 begin
	  if((!int)&&flag[1]&&flag[0]&&(!clear))
		begin
        i<=i+1;
	     if(i>=1105919)            			      //测量结束
		    begin
	        i<=0; 										   //标准时钟计数器清零
		     int<=1;									   //测量结束标志置高
		    end
	    end
     if(flag[1]&&(!flag[0])&&clear)				    //传输结束后，清零测量结束标志
	       int<=0;
   end

always@(flag or CS[2] or int)							 //分三次传输测量数据
  begin
  if(!CS[2]&&int)
   begin
   if(flag==2'b00)
	 adbuff<=j[7:0];
	else if(flag==2'b01)
    adbuff<=j[15:8];
	else if(flag==2'b10)
	 adbuff<=j[23:16];
	 else 
	 adbuff<=8'bzzzzzzzz;
    end
	end 

  always @(ALE)
    begin
    if(ALE)
	 aout<=ad;
    end

 always@(RD or WR or A)
   begin
     case(A)
	 3'b100:
	 begin
	  CS<=4'b0110;
	  en<=1;
	 end
	   3'b101:
	 begin
	  CS<=4'b0110;
	  en<=1;
	 end
	  3'b110:
	 begin
	  CS<=4'b0110;
	  en<=1;
	 end
	  3'b111:
	 begin
	  CS<=4'b0110;
	  en<=1;
	 end
	 3'b010:
	 begin
     CS<=4'b1010;
	  en<=1;	
	 end
    3'b000:
	 begin
     CS<=4'b1100;
	  en<=1;
	 end
     3'b001:
	 begin
	  en<=1;
	  CS[3:1]<=3'b111;
	  CS[0]<=~(RD&WR);
	 end
     3'b011:
	 begin
     CS<=4'b1110;
	  en<=0;
	 end
	 default:
	 begin
	  CS<=4'b1110;
	  en<=1;
	 end
	 endcase
   end
  
 always@(WR)
   begin
 	 if((en|WR)==0)
	  begin
	   lk<=ad[7:4];
	   flag[1:0]<=ad[3:2];	 //写入要读的数值部分
	  end
	 end

 assign  ad=((~CS[2])&(~RD))?adbuff:8'bzzzzzzzz;
 assign  ad[3:0]=((~RD)&(~en))?hk:4'bzzzz;


 endmodule