yx.npl

实现音乐播放的FPGA的实验源码（Verilog语言）

JDF G
// Created by Project Navigator ver 1.0
PROJECT yx
DESIGN yx
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s100
DEVICETIME 1137110316
DEVPKG tq144
DEVPKGTIME 1137110316
DEVSPEED -6
DEVSPEEDTIME 1137121141
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE song.v
DEPASSOC song song.ucf
[STATUS-ALL]
song.ngcFile=WARNINGS,1157090849
[STRATEGY-LIST]
Normal=True