song.twr

实现音乐播放的FPGA的实验源码（Verilog语言）

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Release 6.3i Trace G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml song song.ncd -o
song.twr song.pcf


Design file:              song.ncd
Physical constraint file: song.pcf
Device,speed:             xc2s100,-6 (PRODUCTION 1.27 2004-06-25)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
seg<0>      |    6.345(R)|clk_BUFGP         |   0.000|
seg<1>      |    6.336(R)|clk_BUFGP         |   0.000|
seg<2>      |    6.345(R)|clk_BUFGP         |   0.000|
seg<3>      |    6.336(R)|clk_BUFGP         |   0.000|
seg<4>      |    6.336(R)|clk_BUFGP         |   0.000|
seg<6>      |    6.336(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    8.875|         |         |         |
---------------+---------+---------+---------+---------+

Analysis completed Sat Feb 18 10:28:04 2006
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Peak Memory Usage: 47 MB