song.par

实现音乐播放的FPGA的实验源码（Verilog语言）

Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

CHOPIN-TRIES::  Sat Feb 18 10:27:57 2006


D:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 song_map.ncd song.ncd
song.pcf 


Constraints file: song.pcf

Loading device database for application Par from file "song_map.ncd".
   "song" is an NCD, version 2.38, device xc2s100, package tq144, speed -6
Loading device for application Par from file 'v100.nph' in environment
D:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolved that GCLKIOB <clk> must be placed at site P88.
Resolved that IOB <speaker> must be placed at site P121.
Resolved that IOB <seg<0>> must be placed at site P58.
Resolved that IOB <seg<1>> must be placed at site P57.
Resolved that IOB <seg<2>> must be placed at site P48.
Resolved that IOB <seg<3>> must be placed at site P49.
Resolved that IOB <seg<4>> must be placed at site P50.
Resolved that IOB <seg<5>> must be placed at site P54.
Resolved that IOB <seg<6>> must be placed at site P56.
Resolved that IOB <seg_scan<0>> must be placed at site P38.
Resolved that IOB <seg_scan<1>> must be placed at site P40.
Resolved that IOB <seg_scan<2>> must be placed at site P46.
Resolved that IOB <index<0>> must be placed at site P30.
Resolved that IOB <index<1>> must be placed at site P31.
Resolved that IOB <index<2>> must be placed at site P41.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            14 out of 92     15%
      Number of LOCed External IOBs   14 out of 14    100%

   Number of SLICEs                   58 out of 1200    4%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897df) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9956af) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file song.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 332 unrouted;       REAL time: 0 secs 

Phase 2: 276 unrouted;       REAL time: 5 secs 

Phase 3: 39 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   28   |  0.127     |  0.485      |
+----------------------------+----------+--------+------------+-------------+
|          clk_6MHz          |   Local  |   14   |  0.931     |  3.054      |
+----------------------------+----------+--------+------------+-------------+
|             carry          |   Local  |   17   |  0.175     |  2.950      |
+----------------------------+----------+--------+------------+-------------+
|           clk_4Hz          |   Local  |   10   |  1.997     |  3.165      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 148


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.046
   The MAXIMUM PIN DELAY IS:                               3.165
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.166

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         214          84          24          10           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  54 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file song.ncd.


PAR done.