song.vhi

实现音乐播放的FPGA的实验源码（Verilog语言）

-- VHDL Instantiation Created from source file song.vhd -- 10:01:07 05/27/2006
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT song
	PORT(
		clk : IN std_logic;
		index : IN std_logic_vector(2 downto 0);          
		speaker : OUT std_logic;
		seg : OUT std_logic_vector(6 downto 0);
		seg_scan : OUT std_logic_vector(2 downto 0)
		);
	END COMPONENT;

	Inst_song: song PORT MAP(
		clk => ,
		speaker => ,
		index => ,
		seg => ,
		seg_scan => 
	);