yuequfasheng.vhd

来自「乐曲发生的程序设计,正确,是我们老师给我们的,大家看看吧」· VHDL 代码 · 共 53 行

library ieee;
use ieee.std_logic_1164.all;

entity yuequfasheng is
   port(RESET:in std_logic;
        HLCLK:IN std_logic_vector(0 to 1);
	   LSCLK:IN std_logic_vector(0 to 1);
        SELECTED:IN std_logic_vector(0 to 1);
        CLK:in std_logic;
	   W:out std_logic;
	    V:out std_logic);

end;

architecture yuequfashengb of yuequfasheng is
         
	 
	    component stime
             port(clk:in std_logic;
		   hlclk:IN std_logic_vector(0 to 1);
		    lsclk:IN std_logic_vector(0 to 1);
                  tout:out std_logic;
			   mout:out std_logic);
         end component;
	    component yuequ
           port(clk:in std_logic;
		        selected:in std_logic_vector(0 to 1);
                  reset:in std_logic;
                  q:out integer range 0 to 5102);
         end component;
    
        component fasheng
             port(a:in integer range 0 to 5102;
                  clk:in std_logic;
                  w:out std_logic;
			   v:out std_logic);
        end component;
 
   signal OUTCLK:std_logic;
   signal MOUTCLK:std_logic;
   signal Q:integer range 0 to 5102;
     begin 

    
	u0: stime port map(CLK,HLCLK,LSCLK,OUTCLK,MOUTCLK); 
	u2: yuequ port map(OUTCLK,SELECTED,RESET,Q);
     u3: fasheng port map(Q,MOUTCLK,W,V);
	
    
  end yuequfashengb;