📄 fasheng.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity fasheng is
port(a:in integer range 0 to 5102;
clk:in std_logic;
w:out std_logic;
v:out std_logic);
end;
architecture fashengb of fasheng is
begin
process(clk,a)
variable b,d: std_logic;
variable c: integer range 0 to 5102;
begin
if clk'event and clk='1' then
if b='0' then
c:=a;
b:='1';
elsif c=0 then
b:='0';
d:=not d;
else
c:=c-1;
end if;
end if;
w<=d;
v<=d;
end process;
end fashengb;
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