📄 usb1regs.h
字号:
;IMPORTANT!!!!!!!!!!!!
;This is a BETA version of Firmware that has not been
;fully tested. PLEASE keep this in mind and use this
;firmware as REFERENCE.
;=======================================
; usb1regs.asm
;
; This file contains the SFR regsiter declarations
; CY7C6372x, 6374x
;
;
;========================================
;
; General Constant Declarations
;
;========================================
BIT0: equ 01h
BIT1: equ 02h
BIT2: equ 04h
BIT3: equ 08h
BIT4: equ 10h
BIT5: equ 20h
BIT6: equ 40h
BIT7: equ 80h
;========================================
;
; SFR Declarations
;
;========================================
; I/O ports
P0_data: equ 00h ; GPIO data port 0
P0.0: equ BIT0
P0.1: equ BIT1
P0.2: equ BIT2
P0.3: equ BIT3
P0.4: equ BIT4
P0.5: equ BIT5
P0.6: equ BIT6
P0.7: equ BIT7
P1_data: equ 01h ; GPIO data port 1
P1.0: equ BIT0
P1.1: equ BIT1
P1.2: equ BIT2
P1.3: equ BIT3
P1.4: equ BIT4
P1.5: equ BIT5
P1.6: equ BIT6
P1.7: equ BIT7
P2_data: equ 02h ; Read only Auxiliary data port 2
VREG_B: equ BIT0
XTALIN_B: equ BIT1
D_NEG_B: equ BIT4
D_POS_B: equ BIT5
P0_interrupt: equ 04h ; Interrupt enable for port 0
IE0.0: equ BIT0
IE0.1: equ BIT1
IE0.2: equ BIT2
IE0.3: equ BIT3
IE0.4: equ BIT4
IE0.5: equ BIT5
IE0.6: equ BIT6
IE0.7: equ BIT7
P1_interrupt: equ 05h ; Interrupt enable for port 1
IE1.0: equ BIT0
IE1.1: equ BIT1
IE1.2: equ BIT2
IE1.3: equ BIT3
IE1.4: equ BIT4
IE1.5: equ BIT5
IE1.6: equ BIT6
IE1.7: equ BIT7
P0_Polarity: equ 06h ; Polarity enable for port 0
POL0.0: equ BIT0
POL0.1: equ BIT1
POL0.2: equ BIT2
POL0.3: equ BIT3
POL0.4: equ BIT4
POL0.5: equ BIT5
POL0.6: equ BIT6
POL0.7: equ BIT7
P1_Polarity: equ 07h ; Polarity enable for port 1
POL1.0: equ BIT0
POL1.1: equ BIT1
POL1.2: equ BIT2
POL1.3: equ BIT3
POL1.4: equ BIT4
POL1.5: equ BIT5
POL1.6: equ BIT6
POL1.7: equ BIT7
P0_Mode0: equ 0Ah ; Mode0 register for port 0
M00.0: equ BIT0
M00.1: equ BIT1
M00.2: equ BIT2
M00.3: equ BIT3
M00.4: equ BIT4
M00.5: equ BIT5
M00.6: equ BIT6
M00.7: equ BIT7
P1_Mode0: equ 0Bh ; Mode0 register for port 1
M01.0: equ BIT0
M01.1: equ BIT1
M01.2: equ BIT2
M01.3: equ BIT3
M01.4: equ BIT4
M01.5: equ BIT5
M01.6: equ BIT6
M01.7: equ BIT7
P0_Mode1: equ 0Ch ; Mode1 register for port 0
M10.0: equ BIT0
M10.1: equ BIT1
M10.2: equ BIT2
M10.3: equ BIT3
M10.4: equ BIT4
M10.5: equ BIT5
M10.6: equ BIT6
M10.7: equ BIT7
P1_Mode1: equ 0Dh ; Mode1 register for port 1
M11.0: equ BIT0
M11.1: equ BIT1
M11.2: equ BIT2
M11.3: equ BIT3
M11.4: equ BIT4
M11.5: equ BIT5
M11.6: equ BIT6
M11.7: equ BIT7
; USB ports
USB_DA: equ 10h ; USB device address assigned by host
ADR0_B: equ BIT0
ADR1_B: equ BIT1
ADR2_B: equ BIT2
ADR3_B: equ BIT3
ADR4_B: equ BIT4
ADR5_B: equ BIT5
ADR6_B: equ BIT6
ADEN_B: equ BIT7
EP0_COUNT: equ 11h ; Endpoint 0 counter register
BYTE_COUNT_MASK:equ 0Fh
EP0_ACK: equ BIT4
DATA_VALID: equ BIT6
DATA01_B: equ BIT7
EP0_MODE: equ 12h ; Endpoint 0 mode register
MODE_MASK: equ 0Fh
ACK_B: equ BIT4
EP0_OUT_B: equ BIT5
EP0_IN_B: equ BIT6
EP0_SETUP_B: equ BIT7
EP1_COUNT: equ 13h ; Endpoint 1 counter register
; Same as EP0
EP1_MODE: equ 14h ; Endpoint 1 mode register
;MODE_MASK: equ 0Fh ; Defined in EP0 MODE
;ACK_B: equ BIT4 ; "
STALL_B: equ BIT7
EP2_COUNT: equ 15h ; Endpoint 2 counter register
; Same as EP0
EP2_MODE: equ 16h ; Endpoint 2 mode register
;MODE_MASK: equ 0Fh ; Defined in EP1 MODE
;ACK_B: equ BIT4 ; "
;STALL_B: equ BIT7 ; "
USB_SCR: equ 1Fh ; USB status and control register
CONTROL0_B: equ BIT0
CONTROL1_B: equ BIT1
CONTROL2_B: equ BIT2
ACTIVITY_B: equ BIT3
USB_PS2_B: equ BIT5
VREG_EN_B: equ BIT6
PS2_PULLUP_B: equ BIT7
;Control bits for USB status and control register(Bits 2:0)
NO_FORCE: equ 00h ;Any mode
FORCE_K: equ 01h ;USB_MODE(D+high,D-low)
FORCE_J: equ 02h ;USB_MODE(D+low,D-high)
FORCE_SE0: equ 03h ;USB_MODE(D-low,D+low)
FORCE_LL: equ 04h ;PS2_MODE(D-low,D+low)
FORCE_LHZ: equ 05h ;PS2_MODE(D-low,D+hiz)
FORCE_HZL: equ 06h ;PS2_MODE(D-hiz,D+low)
FORCE_HZHZ: equ 07h ;PS2_MODE(D-hiz,D+hiz)
; control ports
GIER: equ 20h ; Global interrupt enable
USB_PS2_IE: equ BIT0
128USEC_IE: equ BIT1
1MS_IE: equ BIT2
SPI_IE: equ BIT3
CAPTUREA_IE: equ BIT4
CAPTUREB_IE: equ BIT5
GPIO_IE: equ BIT6
WKUP_IE: equ BIT7
EP_IE: equ 21h ; Endpoint enable register
EP0_IE: equ BIT0
EP1_IE: equ BIT1
EP2_IE: equ BIT2
TIMER_LSB: equ 24h ; free-running Timer LSB
TIMER_MSB: equ 25h ; free-running Timer MSB
WDT: equ 26h ; clear watchdog Timer
CAPTUREA_RISE: equ 40h ; Capture timer A rising edge
CAPTUREA_FALL: equ 41h ; Capture timer A falling edge
CAPTUREB_RISE: equ 42h ; Capture timer B rising edge
CAPTUREB_FALL: equ 43h ; Capture timer B falling edge
CAPTURE_CONFIG: equ 44h ; Capture timer configuration
A_RISE_EN: equ BIT0
A_FALL_EN: equ BIT1
B_RISE_EN: equ BIT2
B_FALL_EN: equ BIT3
FIRST_EDGE: equ BIT7
CAPTURE_STATUS: equ 45h ; Capture timer status
A_RISE_EVENT: equ BIT0
A_FALL_EVENT: equ BIT1
B_RISE_EVENT: equ BIT2
B_FALL_EVENT: equ BIT3
SPI_DATA: equ 60h ; SPI interface data
SPI.0: equ BIT0
SPI.1: equ BIT1
SPI.2: equ BIT2
SPI.3: equ BIT3
SPI.4: equ BIT4
SPI.5: equ BIT5
SPI.6: equ BIT6
SPI.7: equ BIT7
SPI_CONTROL: equ 61h ; SPI interface control
SPI_SEL0: equ BIT0
SPI_SEL1: equ BIT1
SPI_CPHA: equ BIT2
SPI_CPOL: equ BIT3
SPI_MODE0: equ BIT4
SPI_MODE1: equ BIT5
SPI_TBF: equ BIT6
SPI_TCMP: equ BIT7
; control ports
CLOCK_CONFIG: equ F8h ; Clock Configuration
EXT_OSC_EN_B: equ BIT0
INTERNAL_EN_B: equ BIT1
PREC_USB_B: equ BIT2
LVR_DISABLE_B: equ BIT3
WKUP_ADJ0_B: equ BIT4
WKUP_ADJ1_B: equ BIT5
WKUP_ADJ2_B: equ BIT6
EXT_RES_DEL_B: equ BIT7
;wakeup timer settings(Bits 6:4 of Clock Config)
1TWAKE: equ 00h
2TWAKE: equ 10h
4TWAKE: equ 20h
8TWAKE: equ 30h
16TWAKE: equ 40h
32TWAKE: equ 50h
64TWAKE: equ 60h
128TWAKE: equ 70h
SCR: equ FFh ;Staus and Control Register
RUN_B: equ BIT0
INT_EN_SENSE_B: equ BIT2
SUSPEND_B: equ BIT3
LVR_BROUT_B: equ BIT4
BUS_INT_EVENT: equ BIT5
WDR: equ BIT6
IRQ_PEND: equ BIT7
RESET_MASK: equ 70h⌨️ 快捷键说明
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