arch_wzd_demo.gfl

来自「FPGA-CPLD_DesignTool,事例程序3-4」· GFL 代码 · 共 20 行

# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# XAW : PDCL (jhdparse)
# Project -> New Source -> CoreGen IP
__projnav/coregenApp_tcl.rsp
__projnav/coregen.crp
coregen.prj
coregen.fin
# XAW : PDCL (jhdparse)
# XAW : View Verilog Source
DCM1.v
# Verilog : View Verilog Instantiation Template
automake.err
# XAW : View Verilog Source
rocket_IO.v
# Verilog : View Verilog Instantiation Template
automake.err