iq_pn_gen.xst

来自「FPGA-CPLD_DesignTool,事例程序3-4」· XST 代码 · 共 40 行

set -tmpdir .
set -overwrite YES
run
-ifmt VERILOG
-top iq_pn_gen
-p xcv300-bg432-6
-ifn iq_pn_gen.prj
-opt_mode Speed
-opt_level 1
-check_attribute_syntax YES
-keep_hierarchy No
-glob_opt AllClockNets
-write_timing_constraints No
-fsm_extract YES -fsm_encoding Auto
-fsm_fftype D
-mux_extract YES
-resource_sharing YES
-complex_clken YES
-rom_extract Yes
-ram_extract Yes
-ram_style Auto
-mux_style Auto
-decoder_extract YES
-priority_extract YES
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-iobuf YES
-equivalent_register_removal YES
-bufg 4
-max_fanout 100
-register_duplication YES
-register_balancing No
-move_first_stage YES
-move_last_stage YES
-slice_packing YES
-iob auto
-ofn iq_pn_gen
-ofmt NGC