run.do

FPGA-CPLD_DesignTool,事例程序3-4

# Copyright Model Technology, a Mentor Graphics
# Corporation company 2003, - All rights reserved.
# Simulation script for Dataflow tutorial

onbreak {resume}

# create library
if [file exists work] {
    vdel -all
}
vlib work
 
# compile all  source files
vlog gates.v and2.v cache.v memory.v proc.v set.v top.v

# open debugging windows
set PrefDataflow(geometry) 582x378+1+562
set PrefSignals(geometry) 287x249+738+307
set PrefWave(geometry) 682x352+590+614
set PrefSource(geometry) 534x249+746+0
set PrefMain(geometry) 730x503+1+1
view da si wa

# start simulator
vsim top

# wave signals
add wave /top/p/*
add log -r *

# run simulation
run -all