dec_lag3.asm

基于TMS320F2812的AMR+RS编解码+OFDM调制解调源程序。是stand alone运行版本

*****************************************************************************
** Description:    dec_lag3() in  dec_lag3.c                              **
**                                                                         **
** Inputs                                                                  **
**               
**   ar2---Word16  index                                                **
**   ar3---word16  t0_min                                                 **
**   ar4---word16  t0_max                                                 **
**   ar5---word16  i_subfr                                             **
**   ar6---word16  T0_prev                                                                      **
** Outputs:  none                                                         **
**   ar0---word16  *T0                                                     **
**   ar1---Word16  *T0_frac                                                                **
** Return value :                                                    **
**                                                                         **
** Attribute    :       Cycles: 150    Pm: 73                          **
**                      Modified Registers:  all                           **
**                                                                         **
** Programmer   :       xie wei                                      **
*****************************************************************************

  .global _dec_lag3
_dec_lag3: 
    
	mov ah,@ar5            ; if (i_subfr == 0)
	sb  _line_51,NEQ       ;if (sub(index, 197) < 0)
  	mov al,ar2             ;*T0 = sub(index, 112);
    mov ah,al      		   ;*T0_frac = 0;
    sub al,#112
    mov ar0,al
    mov ar1,#0
    cmp ah,#197
	sb  _line_117,GEQ
    add ah,#2            ; *T0 = add(mult(add(index, 2), 10923), 19);
    mov T ,#10923
    mpy acc,T,ah
    LSL acc,#1
	add ah,#19
    mov ar0,ah      
    add ah,ah                     ; i = add(add(*T0, *T0), *T0);
    add ah,ar0 
    mov al,@ar2                    ; *T0_frac = add(sub(index, i), 58);
    sub al,ah
    add al,#58
    mov ar1,al
    b   _line_117, UNC                                                   
_line_51:                     ;if ( sub( sub(tmp_lag, t0_min), 5) > 0)
    mov al,@ar6               ;tmp_lag = add (t0_min, 5);
   	sub al,@ar3
	cmp al,#5 
	sb  _line_72,LEQ            
	mov ah,@ar3
	add ah,#5
    mov @ar6,ah
_line_72:
    mov ah,@ar4           ; if ( sub( sub(t0_max, tmp_lag), 4) > 0)
	sub ah,@ar6      
	cmp ah,#4
	sb  _line_80,LEQ
	mov al,@ar4             ;tmp_lag = sub (t0_max, 4);
	sub al,#4
    mov @ar6,al 
_line_80:
    mov ah,@ar2        ;if (sub(index, 4) < 0)
    cmp ah,#4
	sb  _line_101,GEQ   ; i = sub(tmp_lag, 5);
    mov al,@ar6        	; *T0 = add(i, index);
    sub al,#5           ;*T0_frac = 0;        
    add al,ah
    mov ar0,al
    mov ar1,#0
	b   _line_117,UNC
_line_101:              ;i = add( sub (index, 12), tmp_lag);
                		;*T0 = add (i, 1);                
                		;*T0_frac = 0;    
    mov ah,@ar2
	sub ah,#12
	add ah,@ar6
	add ah,#1
	mov ar0,ah
	mov ar1,#0
                        ; if (sub(index, 12) < 0)
    mov ah,@ar2
    cmp ah,#12
    sb  _line_117,GEQ     
   	sub ah,#5            ;  i = sub(mult(sub(index, 5), 10923), 1);
    mov T,#10923         ;*T0 = add(i, tmp_lag);
    mpy acc,T,ah         ;i = add(add(i, i), i);
    lsl acc,#1           ;*T0_frac = sub(sub(index, 9), i);
    sub ah ,#1
    push ah
    add ah ,@ar6
    mov ar0,ah
    pop ah
    mov al,ah
    add ah,ah
    add ah,al
    mov al,@ar2
    sub al,#9
    sub al,ah
    mov ar1,al
_line_117: 
    LRETR