ezdsp_ram_lnk3.cmd

基于TMS320F2812的AMR+RS编解码+OFDM调制解调源程序。是stand alone运行版本

/*
//
//      TMDX BETA RELEASE
//      Intended for product evaluation purposes
//
//###########################################################################
//
// FILE:	EzDSP_RAM_lnk.cmd
//
// TITLE:	Linker Command File For F2812 eZdsp examples that run out of RAM
//          This linker file assumes the user is booting up in Jump to H0 mode
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.51| 02 Apr 2002 | L.H. | Original Release.
//  0.56| 20 May 2002 | L.H. | No change
//  0.58| 18 Jun 2002 | L.H. | Added codestart section 
//      |             |      | Changed .reset section type to DSECT
//      |             |      | CPU Timer1 and CPU Timer2 are reserved for BIOS/RTOS
// -----|-------------|------|-----------------------------------------------
//###########################################################################
*/
-m mem.map
MEMORY
{
PAGE 0 :

   /* SARAM  H0 is split between PAGE 0 and PAGE 1 */  
   /* PRAMH0     : origin = 0x3F8000, length = 0x001000 */

	PROG(R)		     : origin = 0x3D8000, length = 0x18000
	FLASH_INIT_PROG  : ORIGIN = 0x3F0000, LENGTH = 0x007F80
	CSM_RSVD    	 : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Reserved when CSM is in use. */
	BEGIN_FLASH(R)   : origin = 0x3F7FF6, length = 0x000002
	PASSWORDS		 : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations. */		
	
/*	AMRCODE		: origin = 0x3E8000, length = 0x0FFF0*/
  /* PROG(R)     : origin = 0x3d8000, length = 0x5000
   CODEBOOK(R) : origin = 0x3dd000, length = 0x2000
   CONST(R)    : origin = 0x3df000, length = 0x1000*/

   
   
   
   
   /*  This memory block loaded with the reset vector only if 
       booting from XINTF Zone 7.  Otherwise reset vector is
       fetched from boot ROM. See .reset section below        */
   /* RESET      : origin = 0x3FFFC0, length = 0x000002       */
         
PAGE 1 : 
   /* SARAM                     */     
   M0M1RAM   : origin = 0x000000, length = 0x000800
  /* FIRBUFF	 : origin = 0x000700, length = 0x000100*/
  /* M1RAM     : origin = 0x000400, length = 0x000400

    Peripheral Frame 0:   */
   DEV_EMU    : origin = 0x000880, length = 0x000180
   FLASH_REGS : origin = 0x000A80, length = 0x000060
   CSM        : origin = 0x000AE0, length = 0x000010
   XINTF      : origin = 0x000B20, length = 0x000020
   CPU_TIMER0 : origin = 0x000C00, length = 0x000008
   CPU_TIMER1 : origin = 0x000C08, length = 0x000008		 
   CPU_TIMER2 : origin = 0x000C10, length = 0x000008		 
   PIE_CTRL   : origin = 0x000CE0, length = 0x000020
   PIE_VECT   : origin = 0x000D00, length = 0x000100

   /* Peripheral Frame 1:   */
   ECAN_A     : origin = 0x006000, length = 0x000100
   ECAN_AMBOX : origin = 0x006100, length = 0x000100

   /* Peripheral Frame 2:   */
   SYSTEM     : origin = 0x007010, length = 0x000020
   SPI_A      : origin = 0x007040, length = 0x000010
   SCI_A      : origin = 0x007050, length = 0x000010
   XINTRUPT   : origin = 0x007070, length = 0x000010
   GPIOMUX    : origin = 0x0070C0, length = 0x000020
   GPIODAT    : origin = 0x0070E0, length = 0x000020
   ADC        : origin = 0x007100, length = 0x000020
   EV_A       : origin = 0x007400, length = 0x000040
   EV_B       : origin = 0x007500, length = 0x000040
   SPI_B      : origin = 0x007740, length = 0x000010
   SCI_B      : origin = 0x007750, length = 0x000010
   MCBSP_A    : origin = 0x007800, length = 0x000040

   /* CSM Password Locations */
   CSM_PWL    : origin = 0x3F7FF8, length = 0x000008

   /* SARAM  H0 is split between PAGE 0 and PAGE 1 */     
   /* DRAMH0     : origin = 0x3f9000, length = 0x001000  */
   L0L1RAM(RW) : origin = 0x008000, length = 0x001F00
   RAM_INIT	   : ORIGIN = 0x009F00, LENGTH = 0x000100
   
   BEGIN_H0    : origin = 0x3F8000, length = 0x000002     /* Part of H0.  Used for "boot to H0" bootloader mode. */
   H0RAM(RW)   : origin = 0x3f8002, length = 0x001FFE

}
 
 
SECTIONS
{
   /* Allocate program areas: */
  /* 	RamFunc    : > H0RAM,        PAGE = 1*/
   /* Setup for "boot to H0" mode: 
      The codestart section (found in CodeStartBranch.asm)
      re-directs execution to the start of user code.  
      Place this section or the .text section at the
      start of H0  */
   
   /* Allocate data areas: */
   /*
   .stack           : > RAMM1,       PAGE = 1
   .bss             : > DRAMH0,      PAGE = 1
   .ebss            : > DRAMH0,      PAGE = 1
   .const           : > DRAMH0,      PAGE = 1
   .econst          : > DRAMH0,      PAGE = 1      
   .sysmem          : > DRAMH0,      PAGE = 1
   */
    buf1     : > L0L1RAM,           PAGE = 1            /*M1RAM, PAGE = 1*/
    buf2     : > L0L1RAM,           PAGE = 1  
    buf3     : > L0L1RAM,           PAGE = 1
    buf4     : > L0L1RAM,           PAGE = 1
    volt2	 : > L0L1RAM,			  PAGE = 1
   	/*volt3	 : > L0L1RAM,			  PAGE = 1*/
   /*	volt4    : > L0L1RAM,		PAGE = 1	*/
   .bss      : > L0L1RAM,           PAGE = 1
   .ebss     : > H0RAM,           PAGE = 1
   
   .stack    : > M0M1RAM,         PAGE = 1
   .sysmem   : > M0M1RAM,         PAGE = 1
  /* firldb	 : > FIRBUFF,		  PAGE = 1*/
   /* .reset indicates the start of _c_int00 for C Code.  
   /* When using the boot ROM this section is not needed.  
   /* Thus, the default type is set to DESECT */ 
   /* .reset           : > RESET,      PAGE = 0, TYPE = DSECT */
   
   /* Allocate Peripheral Frame 0 Register Structures:   */
   DevEmuRegsFile    : > DEV_EMU,    PAGE = 1
   FlashRegsFile     : > FLASH_REGS, PAGE = 1
   CsmRegsFile       : > CSM,        PAGE = 1
   XintfRegsFile     : > XINTF,      PAGE = 1
   CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1  

   /* CPU_TIMER1 and CPU_TIMER2 are reserved for DSP BIOS
      and RTOS use.  Therefore these sections are not
      allocated in these examples 
   CpuTimer1RegsFile : > CPU_TIMER1, PAGE = 1      
   CpuTimer2RegsFile : > CPU_TIMER2, PAGE = 1
   */
      
   PieCtrlRegsFile   : > PIE_CTRL,   PAGE = 1      
   PieVectTable      : > PIE_VECT,   PAGE = 1

   /* Allocate Peripheral Frame 2 Register Structures:   */
   ECanaRegsFile     : > ECAN_A,      PAGE = 1   
   ECanaMboxesFile   : > ECAN_AMBOX   PAGE = 1

   /* Allocate Peripheral Frame 1 Register Structures:   */
   SysCtrlRegsFile   : > SYSTEM,     PAGE = 1
   SpiaRegsFile      : > SPI_A,      PAGE = 1
   SciaRegsFile      : > SCI_A,      PAGE = 1
   XIntruptRegsFile  : > XINTRUPT,   PAGE = 1
   GpioMuxRegsFile   : > GPIOMUX,    PAGE = 1
   GpioDataRegsFile  : > GPIODAT     PAGE = 1
   AdcRegsFile       : > ADC,        PAGE = 1
   EvaRegsFile       : > EV_A,       PAGE = 1
   EvbRegsFile       : > EV_B,       PAGE = 1
   ScibRegsFile      : > SCI_B,      PAGE = 1
   McbspaRegsFile    : > MCBSP_A,    PAGE = 1

   /* CSM Password Locations */
   CsmPwlFile      : > CSM_PWL,     PAGE = 1
   
 /*  .boot > M0RAM
   {
       rts2800_ml.lib <boot.obj> (.text)
       rts2800_ml.lib <exit.obj> (.text)
       rts2800_ml.lib <_lock.obj> (.text)
       adc_pwm.obj (.text)
    }*/
 
   
  /*
   .reset      : > RESET,    PAGE = 0
   */
   .text       : > PROG,     PAGE = 0
   .pinit      : > PROG,     	PAGE = 0
   .cinit      : > PROG,    	PAGE = 0
   /*.data       : > CODEBOOK, PAGE = 0*/
   .data       : > PROG,    	PAGE = 0
   .const      : > PROG,    	PAGE = 0
   .econst     : > PROG,    	PAGE = 0
   .switch		: > PROG,		PAGE = 0
   
/*** User Defined Sections ***/
   codestart         : > BEGIN_FLASH,     			PAGE = 0                /* Used by file CodeStartBranch.asm */
   csm_rsvd          : > CSM_RSVD,       			PAGE = 0                /* Used by file passwords.asm */
   passwords         : > PASSWORDS,       			PAGE = 0                /* Used by file passwords.asm */
   secureRamFuncs    :   LOAD = FLASH_INIT_PROG,  	PAGE = 0                /* Used by InitFlash() in SysCtrl.c */ 
                         RUN = RAM_INIT, 			PAGE = 1 
                         LOAD_START(_secureRamFuncs_loadstart),
                         LOAD_END(_secureRamFuncs_loadend),
                         RUN_START(_secureRamFuncs_runstart)
  
}