📄 issue.c
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case INT_OP: sprintf(Vj, "%d", *((int *)&(opPtr->source1[0])) = *((int *)&(opPtr2->result[0]))); break; case SFP_OP: sprintf(Vj, "%f", *((float *)&(opPtr->source1[0])) = *((float *)&(opPtr2->result[0]))); break; case DFP_OP: sprintf(Vj, "%f", *((double *)&(opPtr->source1[0])) = *((double *)&(opPtr2->result[0]))); break; } GenEightBit(Vj); } else { sprintf(w, "1.tom.c.%s%d ", functionTypes[unitType], i); GenUpdateStruct(machPtr, "", machPtr->cycleDisplayMode, SHOW_LINE, machPtr->cycleCount, machPtr->cycleCount, w, "", "", "", ""); switch (rs1Type) { case INT_OP: sprintf(Vj, "%d", *((int *)&(opPtr->source1[0])) = *((int *)&(machPtr->regs[wordPtr->rs1]))); break; case SFP_OP: sprintf(Vj, "%f", *((float *)&(opPtr->source1[0])) = *((float *)&(machPtr->regs[wordPtr->rs1]))); break; case DFP_OP: sprintf(Vj, "%f", *((double *)&(opPtr->source1[0])) = *((double *)&(machPtr->regs[wordPtr->rs1]))); break; } GenEightBit(Vj); strcat(msg, Vj); strcat(msg, Qblank); } } else { strcat(msg, " "); sprintf(Vj, " "); } if (rs2Type != NON_OP && rs2Type != IMM_OP) { opPtr->rs2 = wordPtr->rs2; if (machPtr->waiting_regs[wordPtr->rs2]) { opPtr->rs2Ready = machPtr->waiting_regs[wordPtr->rs2] + 1; if (execBegin < opPtr->rs2Ready) execBegin = opPtr->rs2Ready; opPtr2 = WhichOp(machPtr, wordPtr->rs2); strcat(msg, Vblank); sprintf(Qk, "%s ", Units[opPtr2->unit]); strcat(msg, Qk); switch (rs2Type) { case INT_OP: sprintf(Vk, "%d", *((int *)&(opPtr->source2[0])) = *((int *)&(opPtr2->result[0]))); break; case SFP_OP: sprintf(Vk, "%f", *((float *)&(opPtr->source2[0])) = *((float *)&(opPtr2->result[0]))); break; case DFP_OP: sprintf(Vk, "%f", *((double *)&(opPtr->source2[0])) = *((double *)&(opPtr2->result[0]))); break; } GenEightBit(Vk); } else { sprintf(w, "2.tom.c.%s%d ", functionTypes[unitType], i); GenUpdateStruct(machPtr, "", machPtr->cycleDisplayMode, SHOW_LINE, machPtr->cycleCount, machPtr->cycleCount, w, "", "", "", ""); switch (rs2Type) { case INT_OP: sprintf(Vk, "%d", *((int *)&(opPtr->source2[0])) = *((int *)&(machPtr->regs[wordPtr->rs2]))); break; case SFP_OP: sprintf(Vk, "%f", *((float *)&(opPtr->source2[0])) = *((float *)&(machPtr->regs[wordPtr->rs2]))); break; case DFP_OP: sprintf(Vk, "%f", *((double *)&(opPtr->source2[0])) = *((double *)&(machPtr->regs[wordPtr->rs2]))); break; } GenEightBit(Vk); strcat(msg, Vk); strcat(msg, Qblank); } } else { strcat(msg, Vblank); strcat(msg, Qblank); sprintf(Vk, " "); } opPtr->rdReady = execBegin + latency; if (machPtr->opsList == NULL || opPtr->rdReady < machPtr->opsList->rdReady) { opPtr->nextPtr = machPtr->opsList; machPtr->opsList = opPtr; } else { /* POSSIBLE BUG. might want to use a loop to check this condition See how multiple write requests to write ports is checked in BASICPIPE case. */ if (opPtr->rdReady == machPtr->opsList->rdReady && rdType != NON_OP) opPtr->rdReady++; for (opPtr2 = machPtr->opsList; opPtr2->nextPtr != NULL; opPtr2 = opPtr2->nextPtr) { if (opPtr->rdReady < opPtr2->nextPtr->rdReady) break; if (opPtr->rdReady == opPtr2->nextPtr->rdReady && rdType != NON_OP) opPtr->rdReady++; } opPtr->nextPtr = opPtr2->nextPtr; opPtr2->nextPtr = opPtr; } machPtr->func_units[unitType][i] = opPtr->rdReady; if (load_store) { opPtr->address = opPtr->source1[0] + wordPtr->extra; if (unitType == LOAD_BUF) sprintf(msg, "(0x%08x)", opPtr->address); else if (unitType == STORE_BUF) sprintf(msg, "%s(0x%08x)", &msg[22], opPtr->address); } sprintf(w, ".tom.c.%s%d ", functionTypes[unitType], i); GenUpdateStruct(machPtr, w, machPtr->cycleDisplayMode, INSERT_HIGHLIGHT, machPtr->cycleCount, opPtr->rdReady, msg, "", "", "", ""); GenUpdateStruct(machPtr, "", machPtr->cycleDisplayMode, SHOW_LINE, machPtr->cycleCount, machPtr->cycleCount, "i", w, "", "", ""); sprintf(msg, "%-20.20s", Asm_Disassemble(machPtr, machPtr->memPtr[machPtr->regs[PC_REG]].value, Sim_GetPC(machPtr) & ~0x3)); GenUpdateStruct(machPtr, ".tom.c.instr ", machPtr->cycleDisplayMode, DELETE_INSERT, machPtr->cycleDisplayCount, machPtr->cycleCount, msg, "", "", "", ""); if (latency == 1) sprintf(part1, "%8d %8d ", machPtr->cycleCount, execBegin); else sprintf(part1, "%8d %8d-%-8d ", machPtr->cycleCount, execBegin, opPtr->rdReady - 1); strcat(msg, part1); sprintf(part1, "%-8d", opPtr->rdReady); strcat(msg, part1); GenUpdateStruct(machPtr, ".tom.c.frame.table ", machPtr->cycleDisplayMode, ADD_END, machPtr->cycleCount, machPtr->cycleCount, msg, "", "", "", ""); if (machPtr->cycleCount < opPtr->rs1Ready || machPtr->cycleCount < opPtr->rs2Ready) { if (!load_store) { if (machPtr->cycleCount < opPtr->rs1Ready && opPtr->rs1Ready < opPtr->rs2Ready) { GenUpdateStruct(machPtr, w, 1, DELETE_INSERT, opPtr->rs1Ready, opPtr->rdReady, OpCode, Vj, Qblank, Vblank, Qk); } else if (machPtr->cycleCount < opPtr->rs2Ready && opPtr->rs2Ready < opPtr->rs1Ready) { GenUpdateStruct(machPtr, w, 1, DELETE_INSERT, opPtr->rs2Ready, opPtr->rdReady, OpCode, Vblank, Qj, Vk, Qblank); } GenUpdateStruct(machPtr, w, 1, DELETE_INSERT, execBegin, opPtr->rdReady, OpCode, Vj, Qblank, Vk, Qblank); } else if (unitType == STORE_BUF) { sprintf(msg, "(0x%08x)", opPtr->address); GenUpdateStruct(machPtr, w, 1, DELETE_INSERT, opPtr->rs2Ready, opPtr->rdReady, Vk, Qblank, msg, "", ""); } } opPtr->rd = wordPtr->rd; if (rdType && wordPtr->rd) { sprintf(msg, ".tom.c.%s%d", functionTypes[unitType], i); GenUpdateStruct(machPtr, w, 1, SHOW_CDB_LINE, opPtr->rdReady, opPtr->rdReady, msg, "", "", "", ""); machPtr->waiting_regs[wordPtr->rd] = opPtr->rdReady; machPtr->Qi_regs[wordPtr->rd] = opPtr->unit; sprintf(w, ".tom.c.reg%d ", wordPtr->rd); GenUpdateStruct(machPtr, w, machPtr->cycleDisplayMode, INSERT_HIGHLIGHT, machPtr->cycleCount, opPtr->rdReady, Units[opPtr->unit], "", "", "", ""); if (rdType == DFP_OP) { machPtr->waiting_regs[wordPtr->rd + 1] = opPtr->rdReady; machPtr->Qi_regs[wordPtr->rd + 1] = opPtr->unit; sprintf(w, ".tom.c.reg%d ", wordPtr->rd + 1); GenUpdateStruct(machPtr, w, machPtr->cycleDisplayMode, INSERT_HIGHLIGHT, machPtr->cycleCount, opPtr->rdReady, Units[opPtr->unit], "", "", "", ""); } } break; } case SCOREBOARD: { char OpCode[20], Qj[10], Qk[10], Rj[10], Rk[10], w[20], temp[10]; char *Qblank = " "; int readBegin; machPtr->cycleDisplayCount = machPtr->cycleCount; switch (unitType) { case LOAD_BUF: case STORE_BUF: load_store = 1; case INT: case BRANCH: unitType = INT; num_units = machPtr->num_int_units; latency = machPtr->int_latency; break; case FP_ADD: num_units = machPtr->num_add_units; latency = machPtr->fp_add_latency; break; case FP_MUL: num_units = machPtr->num_mul_units; latency = machPtr->fp_mul_latency; break; case FP_DIV: latency = machPtr->fp_div_latency; if (machPtr->fp_div_exist) { num_units = machPtr->num_div_units; } else { unitType = FP_MUL; num_units = machPtr->num_mul_units; } break; } issueCheck2: wait = 0; if (rdType != NON_OP && machPtr->waiting_regs[wordPtr->rd]) wait = machPtr->waiting_regs[wordPtr->rd]; for (i = 0, soonest = 0x7fffffff; i < num_units; i++) { if (!(j = machPtr->func_units[unitType][i])) break; else if (j < soonest) soonest = j; } if (i == num_units && (soonest > wait)) wait = soonest; if (wait) { /* machPtr->stalls = wait - machPtr->cycleCount + 1; */ machPtr->cycleCount = wait; Isu_WriteBack(machPtr); machPtr->cycleCount++; goto issueCheck2; } Tcl_VarEval(machPtr->interp, ".sco.c delete thickLine", (char *)NULL); opPtr = mallocOp(machPtr); opPtr->rs1 = -1; opPtr->rs2 = -1; opPtr->rs1Ready = machPtr->cycleCount + 1; opPtr->rs2Ready = machPtr->cycleCount + 1; while (!machPtr->cycleDisplayMode && machPtr->updateList != NULL && machPtr->updateList->displayCycle <= machPtr->cycleCount) { updatePtr = machPtr->updateList; machPtr->updateList = updatePtr->nextPtr; if (updatePtr->readyCycle >= machPtr->cycleCount) { Tcl_SetVar(machPtr->interp, "msg", updatePtr->msg, TCL_GLOBAL_ONLY); if (updatePtr->actionType == DELETE_INSERT) { Tcl_VarEval(machPtr->interp, "DeleteAndInsert ", updatePtr->w, "$msg", (char *)NULL); } else if (updatePtr->actionType == SHOW_LINE) { Tcl_VarEval(machPtr->interp, "ShowResLine ", "$msg", (char *)NULL); } else if (updatePtr->actionType == HIGHLIGHT_WRITE) { Tcl_VarEval(machPtr->interp, "HighLightWrite ", updatePtr->w, (char *)NULL); } } Isu_FreeUpdate(machPtr, updatePtr); } sprintf(w, "%d", wordPtr->line); GenUpdateStruct(machPtr, "", machPtr->cycleDisplayMode, HIGHLIGHT_CODE, machPtr->cycleCount, machPtr->cycleCount, w, "", "", "", ""); sprintf(OpCode, "Yes %-8.8s ", operationNames[wordPtr->opCode]); if (!machPtr->cycleDisplayMode) Tcl_VarEval(machPtr->interp, ".sco.c.counter configure -text $cycleCount; UnHighLight", (char *)NULL); readBegin = machPtr->cycleCount + 1; opPtr->unit = unitType * MAX_FUNC_UNITS + i; opPtr->resultType = rdType; for (j = 0; j < 3; j++) { switch (j) { case 0: regType = rdType; regNumber = wordPtr->rd; break; case 1: regType = rs1Type; regNumber = wordPtr->rs1; break; case 2: regType = rs2Type; regNumber = wordPtr->rs2; break; } switch (regType) { case INT_OP: if (wordPtr->rd != FP_STATUS) sprintf(temp, "R%-2d ", regNumber); else sprintf(temp, "FPS "); break; case SFP_OP: case DFP_OP: sprintf(temp, "F%-2d ", regNumber - 32); break; default: sprintf(temp, " "); } strcat(OpCode, temp); } strcpy(msg, OpCode); sprintf(Qj, Qblank); sprintf(Rj, "Yes "); if (rs1Type != NON_OP && rs1Type != IMM_OP) { opPtr->rs1 = wordPtr->rs1; if (machPtr->waiting_regs[wordPtr->rs1]) { opPtr->rs1Ready = machPtr->waiting_regs[wordPtr->rs1] + machPtr->sameCycle_regs[wordPtr->rs1] + 1; readBegin = opPtr->rs1Ready; machPtr->sameCycle_regs[wordPtr->rs1]++; opPtr2 = WhichOp(machPtr, wordPtr->rs1); if (machPtr->cycleCount != machPtr->waiting_regs[wordPtr->rs1]) { sprintf(Qj, "%s ", Units[opPtr2->unit]); sprintf(Rj, "No "); } switch (rs1Type) { case INT_OP: *((int *)&(opPtr->source1[0])) = *((int *)&(opPtr2->result[0])); break; case SFP_OP: *((float *)&(opPtr->source1[0])) = *((float *)&(opPtr2->result[0])); break; case DFP_OP: *((double *)&(opPtr->source1[0])) = *((double *)&(opPtr2->result[0])); break; } } else { switch (rs1Type) { case INT_OP: *((int *)&(opPtr->source1[0])) = *((int *)&(machPtr->regs[wordPtr->rs1])); break; case SFP_OP: *((float *)&(opPtr->source1[0])) = *((float *)&(machPtr->regs[wordPtr->rs1])); break; case DFP_OP: *((double *)&(opPtr->source1[0])) = *((double *)&(machPtr->regs[wordPtr->rs1])); break; } } sprintf(w, "1.sco.c.%s%d ", functionTypes[unitType], i); GenUpdateStruct(machPtr, "", 1, SHOW_LINE, opPtr->rs1Ready, opPtr->rs1Ready, w, "", "", "", ""); } strcat(msg, Qj); sprintf(Qk, Qblank); sprintf(Rk, "Yes "); if (rs2Type != NON_OP && rs2Type != IMM_OP) { opPtr->rs2 = wordPtr->rs2; if (machPtr->waiting_regs[wordPtr->rs2]) { opPtr->rs2Ready = machPtr->waiting_regs[wordPtr->rs2] + machPtr->sameCycle_regs[wordPtr->rs2] + 1; if (readBegin < opPtr->rs2Ready) { if (opPtr->rs1Ready) machPtr->sameCycle_regs[wordPtr->rs1]--; readBegin = opPtr->rs2Ready; machPtr->sameCycle_regs[wordPtr->rs2]++; } opPtr2 = WhichOp(machPtr, wordPtr->rs2); if (machPtr->cycleCount != machPtr->waiting_regs[wordPtr->rs2]) { sprintf(Qk, "%s ", Units[opPtr2->unit]); sprintf(Rk, "No "); } switch (rs2Type) { case INT_OP: *((int *)&(opPtr->source2[0])) = *((int *)&(opPtr2->result[0])); break; case SFP_OP: *((float *)&(opPtr->source2[0])) = *((float *)&(opPtr2->result[0])); break; case DFP_OP: *((double *)&(opPtr->source2[0])) = *((double *)&(opPtr2->result[0])); break; } } else { opPtr->rs2Ready = machPtr->cycleCount + 1; switch (rs2Type) { case INT_OP: *((int *)&(opPtr->source2[0])) = *((int *)&(machPtr->regs[wordPtr->rs2])); break; case SFP_OP: *((float *)&(opPtr->source2[0])) = *((float *)&(machPtr->regs[wordPtr->rs2])); break; case DFP_OP: *((double *)&(opPtr->source2[0])) = *((double *)&(machPtr->regs[wordPtr->rs2])); break; } } sprintf(w, "2.sco.c.%s%d ", functionTypes[unitType], i); GenUpdateStruct(machPtr, "", 1, SHOW_LINE, opPtr->rs2Ready, opPtr->rs2Ready, w, "", "", "", ""); } strcat(msg, Qk); strcat(msg, Rj); strcat(msg, Rk); opPtr->rd = wordPtr->rd; opPtr->rdReady = readBegin + latency + 1; /* check for WAR hazard */ if (rdType && wordPtr->rd) { int readBegin2; wait = opPtr->rdReady; for (opPtr2 = machPtr->opsList; opPtr2 != NULL; opPtr2 = opPtr2->nextPtr) { readBegin2 = (opPtr2->rs1Ready > opPtr2->rs2Ready) ? opPtr2->rs1Ready : opPtr2->rs2Ready; if ((opPtr2->rs1 == opPtr->rd || opPtr2->rs2 == opPtr->rd) && opPtr->rdReady < readBegin2 + 1 && wait < readBegin2 + 1)
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