dlx.h

计算机系统结构的讲义,浓缩了一本一千多页的书.真的是好东西.

/*
 * dlx.h --
 *
 *  Declarations of structures used to simulate the DLX
 *  architecture.
 *
 *  This file is part of DISC.  It was modified by Yinong Zhang 
 *  ([e-mail]) from the file "dlx.h" in the distribution
 *  of "dlxsim" available at:
 *     ftp://max.stanford.edu/pub/hennessy-patterson.software/dlx.tar.Z
 *
 *  The original source code is copyright as follows:
 *
 * Copyright 1989 Regents of the University of California
 * Permission to use, copy, modify, and distribute this
 * software and its documentation for any purpose and without
 * fee is hereby granted, provided that the above copyright
 * notice appear in all copies.  The University of California
 * makes no representations about the suitability of this
 * software for any purpose.  It is provided "as is" without
 * express or implied warranty.
 *
 */

#ifndef _MIPS
#define _MIPS

#define MEMSIZE 16384

#ifndef _TCL
#include <tcl.h>
#endif
#ifndef _MIPSIM_IO
#include "io.h"
#endif
#ifndef _COP0
#include "cop0.h"
#endif


/*
 * The following structure is used for each "stop" that has
 * been requested for a machine.
 */

typedef struct Stop {
    char *command;		/* Tcl command to execute, or NULL if
				 * this is a simple stop. */
    int number;			/* Number that identifies this stop for
				 * deletion purposes. */
    unsigned int address;	/* Address (in DLX memory) of memory word
				 * associated with stop. */
    struct Stop *nextPtr;	/* Next in list of stops associated with
				 * same memory location (NULL for end of
				 * list). */
    struct Stop *overallPtr;	/* Next in list of all stops set for
				 * machine (NULL for end of list). */
} Stop;

/*
 * Each memory word is represented by a structure of the following
 * format.  In order to interpret instructions efficiently, they
 * get decoded into several fields on the first execution after each
 * change to the word.
 */

typedef struct {
    int value;			/* Contents of the memory location. */
    int opCode;		/* Type of instruction.  This is NOT
				 * the same as the opcode field from the
				 * instruction:  see #defines below
				 * for details. */
    int rs1, rs2, rd;		/* Three registers from instruction. */
    int extra;			/* Immediate or target or shamt field
				 * or offset.  Immediates are sign-extended. */
    int line;                   /* Line in which the instruction is displayed
				   in the .code.t window. */
    Stop *stopList;		/* List of stops to invoke whenever
				 * this memory location is accessed. */
} MemWord;

/*
 * For each callback registered through Sim_CallBack, there is a structure
 * of the following form:
 */

typedef struct CallBack {
    int serialNum;		/* Call the procedure after executing the
				 * instruction with this serial number. */
    void (*proc)();		/* Procedure to call. */
    ClientData clientData;	/* Argument to pass to proc. */
    struct CallBack *nextPtr;	/* Next callback in list of all those
				 * associated with this machine.  NULL
				 * means end of list. */
} CallBack;



/*
 * For each pending floating point operation, there is a structure of the
 * following form:
 */

typedef struct Op {
  int rs1, rs2;                /* source register, only used in scorboarding
				  algorithm for check WAR hazards. */
  int rs1Ready, rs2Ready;      /* cycle when operands are available. */
  int source1[2], source2[2];  /* source values. */
  int rd;                      /* destination register */
  int rdReady;                 /* cycle when result will be ready */
  int result[2];               /* result[0] is result of single precision
				  operation, both elements used for double
				  precision.
				  A single precision float, and a long
				  integer must be the same size.  */
  int resultType;              /* see *_OP values */
  int unit;                    /* function unit */
  unsigned int address;	       /* mem address of  load or store for 
				* load/store buffer in Tomasulo and Scoreboard Alg. */
  struct Op *nextPtr;          /* Next Op in the list of all those
				* associated with this machine.  NULL
				* means end of list. */
} Op;




/*
 * For each cycle, the structure of data for result buffers and memory
 * data register in basic pipeline configuration has the following form:
 */

typedef struct Bypass {
  int buffer;                  /* can be RESULT_BUF1,RESULT_BUF2, MEM_BUF */
  int displayCycle;            /* clock cycle to display the contents in the buffer */
  int reg;		       /* destination register for the buffer */
  struct Bypass *nextPtr;      /* Next Bypass buffer in the list of all those
				* associated with this machine.  NULL
				* means end of list. */
} Bypass;


/*
 * For each cycle, the structure of data for result buffers and memory
 * data register in basic pipeline configuration has the following form:
 */

typedef struct Update {
  int displayCycle;            /* clock cycle to update the information. */
  int readyCycle;	       /* clock cycle when the instruction finishes. */
  int actionType;	       /* type of updating action at display cycle. */
  char w[30];                  /* text widget name of the unit to be updated 
				* Tomasulot and Scoreboarding, tag id of 
				* items on canvas in BasicPipe.*/
                         
  char msg[80];		       /* string to update the old information in
				  function unit display. */
  struct Update *nextPtr;      /* Next functional unit or reservation station in the
				* list of all those associated with this machine.  NULL
				* means end of list. */
} Update;






/*
 * The structure below describes the state of an DLX machine.
 */
#define TOTAL_REGS 67
#define NUM_GPRS 64
#define FP_STATUS (NUM_GPRS)
#define PC_REG (NUM_GPRS+1)
#define NEXT_PC_REG (NUM_GPRS+2)

/* default values for number of fp units and latencies */
#define MAX_FUNC_UNITS  8       /* Maximum allowable number of any 
				   type of function unit. */
#define NUM_INT_UNITS 1         /* Number of interger units. */
#define NUM_ADD_UNITS 2         /* Number of fp adder units. */
#define NUM_DIV_UNITS 2         /* Number of fp divider units. */
#define NUM_MUL_UNITS 2         /* Number of fp multiplier units. */
#define NUM_LOAD_BUFS 6		/* Number of load buffer (Tomasulo). */
#define NUM_STORE_BUFS 3	/* Number of store buffer (Tomasulo). */
#define INT_LATENCY 1           /* Latency of integer unit */
#define FP_ADD_LATENCY 2        /* Latency for an FP add. */
#define FP_DIV_LATENCY 19       /* Latency for an FP divide. */
#define FP_MUL_LATENCY 5        /* Latency for an FP multiply. */
#define LOAD_BUF_LATENCY 2     	/* Latency for a load buf (Tomasulo). */
#define STORE_BUF_LATENCY 2	/* Latency for a store buf (Tomasulo). */

#define BASICPIPE 0
#define TOMASULO 1
#define SCOREBOARD 2

#define INT 0
#define FP_ADD 1
#define FP_DIV 2
#define FP_MUL 3
#define LOAD_BUF 4
#define STORE_BUF 5
#define BRANCH 6
#define REG_FILE 7

#define NON_OP 0
#define INT_OP 1
#define SFP_OP 2
#define DFP_OP 3
#define IMM_OP 4

#define RESULT_BUF1 1
#define RESULT_BUF2 2
#define RESULT_BUF3 3
#define MEM_BUF0 4
#define MEM_BUF1 5
#define RESULT_BUF1_FP 6
#define RESULT_BUF2_FP 7

#define INSERT_HIGHLIGHT 0
#define HIGHLIGHT_CODE 1
#define DELETE_INSERT 2
#define ADD_END 3
#define HIGHLIGHT_WRITE 4
#define SHOW_CDB_LINE 5
#define SHOW_LINE 6
#define BAS_HIGHLIGHT_LINE 7
#define BAS_HIGHLIGHT_TEXT 8
#define BAS_HIGHLIGHT_RECT 9

#define CYC_CNT_RESET 16384     /* How often to reset the cycle count to
				   prevent wrap around problems. */
#define FD_SIZE 32              /* Number of simulated file descriptors */

/*
 * OpCode values for MemWord structs.  These are straight from the MIPS
 * manual except for the following special values:
 *
 * OP_NOT_COMPILED -	means the value of the memory location has changed
 *			so the instruction needs to be recompiled.
 * OP_UNIMP -		means that this instruction is legal, but hasn't
 *			been implemented in the simulator yet.
 * OP_RES -		means that this is a reserved opcode (it isn't
 *			supported by the architecture).
 */


#define OP_NOP           0
#define OP_ADD 		 1
#define OP_ADDI 	 2
#define OP_ADDU 	 3
#define OP_ADDUI 	 4
#define OP_AND 		 5
#define OP_ANDI 	 6
#define OP_BEQZ 	 7
#define OP_BFPF 	 8
#define OP_BFPT 	 9
#define OP_BNEZ 	 10
#define OP_J 		 11
#define OP_JAL 		 12
#define OP_JALR 	 13
#define OP_JR 		 14
#define OP_LB 		 15
#define OP_LBU 		 16
#define OP_LD 		 17
#define OP_LF 		 18
#define OP_LH 		 19
#define OP_LHI 		 20
#define OP_LHU 		 21
#define OP_LW 		 22
#define OP_MOVD 	 23
#define OP_MOVF 	 24
#define OP_MOVFP2I 	 25
#define OP_MOVI2FP 	 26
#define OP_MOVI2S 	 27
#define OP_MOVS2I 	 28
#define OP_OR 		 29
#define OP_ORI 		 30
#define OP_RFE 		 31
#define OP_SB 		 32
#define OP_SD 		 33
#define OP_SEQ 		 34
#define OP_SEQI 	 35
#define OP_SEQU 	 36
#define OP_SEQUI 	 37
#define OP_SF 		 38
#define OP_SGE 		 39
#define OP_SGEI 	 40
#define OP_SGEU 	 41
#define OP_SGEUI 	 42
#define OP_SGT 		 43
#define OP_SGTI 	 44
#define OP_SGTU 	 45
#define OP_SGTUI 	 46
#define OP_SH 		 47
#define OP_SLE 		 48
#define OP_SLEI 	 49
#define OP_SLEU 	 50
#define OP_SLEUI 	 51
#define OP_SLL 		 52
#define OP_SLLI 	 53
#define OP_SLT 		 54
#define OP_SLTI 	 55
#define OP_SLTU 	 56
#define OP_SLTUI 	 57
#define OP_SNE 		 58
#define OP_SNEI 	 59
#define OP_SNEU 	 60
#define OP_SNEUI 	 61
#define OP_SRA 		 62
#define OP_SRAI 	 63
#define OP_SRL 		 64
#define OP_SRLI 	 65
#define OP_SUB 		 66
#define OP_SUBI 	 67
#define OP_SUBU 	 68
#define OP_SUBUI 	 69
#define OP_SW 		 70
#define OP_TRAP 	 71
#define OP_XOR 		 72
#define OP_XORI 	 73

#define OP_ADDD 	 80
#define OP_ADDF 	 81
#define OP_CVTD2F 	 82