ioswitch.vhd

来自「人民邮电出版社出版的《FPGA硬件接口设计实践》一书的代码」· VHDL 代码 · 共 60 行

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--
-- File        : IOSwitch.vhd
-- Create Time : Thu Apr 22 13:21:49 2004
-- Title       : IOSwitch
-- Design      : USB Interface IP Core
-- Author      : Lou Xinghua ([e-mail])
-- Company     : Department of Engineering Physics in Tsinghua Unversity, Beijing, China
-- Version     : 1.0
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {IOSwitch} architecture {IOSwitch}}

library IEEE;
use IEEE.STD_LOGIC_1164.all;


entity IOSwitch is
	port( 	
		data : inout STD_LOGIC_VECTOR(7 downto 0);
		din : in STD_LOGIC_VECTOR(7 downto 0);
		dout : out STD_LOGIC_VECTOR(7 downto 0);
		sel_in_n : in STD_LOGIC;
		sel_out_n : in STD_LOGIC
	    );
end IOSwitch;

--}} End of automatically maintained section

architecture IOSwitch of IOSwitch is   

signal data_tmp : STD_LOGIC_VECTOR(7 downto 0);

begin

	-- enter your statements here -- 
	
	data <= data_tmp;  
	dout <= data;
	process(sel_in_n, sel_out_n, data, din)
	begin
		if sel_out_n = '0' then
			data_tmp <= "ZZZZZZZZ";	
		elsif sel_in_n = '0' then
			data_tmp <= din;
		else  
			data_tmp <= "ZZZZZZZZ";
		end if;
	end process;
	

end IOSwitch;