i2c_master_bit_ctrl.syr

人民邮电出版社出版的《FPGA硬件接口设计实践》一书的代码

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
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--> Reading design: i2c_master_bit_ctrl.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : i2c_master_bit_ctrl.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : i2c_master_bit_ctrl
Output Format                      : NGC
Target Device                      : xc2s50e-6-tq144

---- Source Options
Top Module Name                    : i2c_master_bit_ctrl
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : i2c_master_bit_ctrl.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "i2c_master_bit_ctrl.v"
Compiling include file "i2c_master_defines.v"
Module <i2c_master_bit_ctrl> compiled
No errors in compilation
Analysis of file <i2c_master_bit_ctrl.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <i2c_master_bit_ctrl>.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 180: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 189: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 190: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 194: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 195: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <i2c_master_bit_ctrl> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <i2c_master_bit_ctrl>.
    Related source file is i2c_master_bit_ctrl.v.
    Found finite state machine <FSM_0> for signal <c_state>.
    -----------------------------------------------------------------------
    | States             | 18                                             |
    | Transitions        | 50                                             |
    | Inputs             | 6                                              |
    | Outputs            | 19                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0001 (positive)                              |
    | Reset              | nReset (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000000000000000001                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <sda_oen>.
    Found 1-bit register for signal <al>.
    Found 1-bit register for signal <cmd_ack>.
    Found 1-bit register for signal <busy>.
    Found 1-bit register for signal <scl_oen>.
    Found 1-bit register for signal <dout>.
    Found 16-bit subtractor for signal <$n0049> created at line 210.
    Found 1-bit register for signal <clk_en>.
    Found 1-bit register for signal <cmd_stop>.
    Found 16-bit register for signal <cnt>.
    Found 1-bit register for signal <dcmd_stop>.
    Found 1-bit register for signal <dSCL>.
    Found 1-bit register for signal <dscl_oen>.
    Found 1-bit register for signal <dSDA>.
    Found 1-bit register for signal <sda_chk>.
    Found 1-bit register for signal <sSCL>.
    Found 1-bit register for signal <sSDA>.
    Found 1-bit register for signal <sta_condition>.
    Found 1-bit register for signal <sto_condition>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <i2c_master_bit_ctrl> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Registers                        : 18
  1-bit register                   : 17
  16-bit register                  : 1
# Adders/Subtractors               : 1
  16-bit subtractor                : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <c_state> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <i2c_master_bit_ctrl> ...
Loading device for application Xst from file '2s50e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c_master_bit_ctrl, actual ratio is 7.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : i2c_master_bit_ctrl.ngr
Top Level Output File Name         : i2c_master_bit_ctrl
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 35

Macro Statistics :
# Registers                        : 18
#      1-bit register              : 17
#      16-bit register             : 1
# Adders/Subtractors               : 1
#      16-bit subtractor           : 1

Cell Usage :
# BELS                             : 136
#      GND                         : 1
#      LUT1                        : 17
#      LUT2                        : 12
#      LUT2_L                      : 1
#      LUT3                        : 21
#      LUT3_L                      : 2
#      LUT4                        : 40
#      LUT4_D                      : 1
#      LUT4_L                      : 9
#      MUXCY                       : 15
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 51
#      FD                          : 1
#      FDC                         : 7
#      FDCE                        : 34
#      FDE                         : 1
#      FDP                         : 5
#      FDPE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 34
#      IBUF                        : 26
#      OBUF                        : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                      59  out of    768     7%  
 Number of Slice Flip Flops:            51  out of   1536     3%  
 Number of 4 input LUTs:               103  out of   1536     6%  
 Number of bonded IOBs:                 34  out of    102    33%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 51    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.421ns (Maximum Frequency: 87.558MHz)
   Minimum input arrival time before clock: 9.040ns
   Maximum output required time after clock: 8.619ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               11.421ns (Levels of Logic = 4)
  Source:            cnt_7 (FF)
  Destination:       cnt_6 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: cnt_7 to cnt_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.992   1.150  cnt_7 (cnt_7)
     LUT4:I0->O            1   0.468   0.920  _n005349 (CHOICE110)
     LUT2_L:I0->LO         1   0.468   0.100  _n005363 (CHOICE118)
     LUT4:I2->O           18   0.468   2.900  _n005394 (_n0053)
     LUT4:I2->O           16   0.468   2.800  _n00651 (_n0065)
     FDCE:CE                   0.687          cnt_0
    ----------------------------------------
    Total                     11.421ns (3.551ns logic, 7.870ns route)
                                       (31.1% logic, 68.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              9.040ns (Levels of Logic = 3)
  Source:            ena (PAD)
  Destination:       cnt_6 (FF)
  Destination Clock: clk rising

  Data Path: ena to cnt_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.797   0.920  ena_IBUF (ena_IBUF)
     LUT4:I3->O           18   0.468   2.900  _n005394 (_n0053)
     LUT4:I2->O           16   0.468   2.800  _n00651 (_n0065)
     FDCE:CE                   0.687          cnt_0
    ----------------------------------------
    Total                      9.040ns (2.420ns logic, 6.620ns route)
                                       (26.8% logic, 73.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              8.619ns (Levels of Logic = 1)
  Source:            al (FF)
  Destination:       al (PAD)
  Source Clock:      clk rising

  Data Path: al to al
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             21   0.992   3.025  al (al_OBUF)
     OBUF:I->O                 4.602          al_OBUF (al)
    ----------------------------------------
    Total                      8.619ns (5.594ns logic, 3.025ns route)
                                       (64.9% logic, 35.1% route)

=========================================================================
CPU : 3.60 / 4.13 s | Elapsed : 4.00 / 4.00 s
 
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Total memory usage is 56716 kilobytes