_primary.vhd

人民邮电出版社出版的《FPGA硬件接口设计实践》一书的代码

library verilog;
use verilog.vl_types.all;
entity can_ibo is
    port(
        di              : in     vl_logic_vector(7 downto 0);
        do              : out    vl_logic_vector(7 downto 0)
    );
end can_ibo;