topt.vhd

用CPLD驱动SJA1000 CAN控制器

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:04:37 05/02/2006 
-- Design Name: 
-- Module Name:    top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
         port(sysclk:     in  std_logic;
			     nreset_3828:in  std_logic;
				  nreset_cpu: out std_logic;
				  
				  cpu_nwe:    in  std_logic;
				  cpu_noe:    in  std_logic;
				  cpu_ncs1:   in  std_logic;
				  cpu_ncs3:   in  std_logic;
				  cpu_ncs5:   in  std_logic;
				  cpu_nwait:  out std_logic;
				  cpu_addr:   in  std_logic_vector(7 downto 0);
				  cpu_addr23: in  std_logic;
				  cpu_addr24: in  std_logic;
				  cpu_data:   inout std_logic_vector(15 downto 0);
				  
--				  --eth
				  eth_nwe:    out std_logic;
				  eth_noe:	  out std_logic;
				  eth_clk:    out std_logic;
				  eth_reset:  out std_logic;
--	
--				  --cf
				  cf_reset:   out std_logic;
--
--				  --CAN
				  can_nreset: out std_logic;
				  can_ale:    out std_logic;
				  cana_ncs:   out std_logic;
				  canb_ncs:   out std_logic;
				  can_wr:     out std_logic;
				  can_rd:     out std_logic;
				  can_dir:    out std_logic;
				  can_ad:     inout std_logic_vector(7 downto 0);
				  
				  --speaker and test_led
				  speaker:    out std_logic;
				  test_led:   out std_logic);			  
end top;

architecture Behavioral of top is
  
  signal led_count:  integer range 0 to 4000000; 
  signal led_buf:    std_logic;
  signal eth_clk_buf:std_logic;
--  signal cpu_nwe_vec:std_logic_vector(2 downto 0);
--  signal cpu_noe_vec:std_logic_vector(2 downto 0);
  
  signal can_en_addr:std_logic;
  signal can_en_data:std_logic;
  signal can_dir_data:std_logic;
  signal can_state:std_logic_vector(1 downto 0);
  signal delay_can:integer range 0 to 7;
  
	
  begin
  process(sysclk)
    begin
	   if sysclk'event and sysclk='1' then
--		  cpu_nwe_vec<=cpu_nwe_vec(1 downto 0) & cpu_nwe;
--		  cpu_noe_vec<=cpu_noe_vec(1 downto 0) & cpu_noe;
		  eth_clk_buf<=not eth_clk_buf;
		  if led_count>=4000000 then
		     led_count<=0;  
		     led_buf<=not led_buf;
		  else 
           led_count<=led_count+1;
        end	if;
      end if;
  end process;	
 
process(sysclk)
begin
  if nreset_3828='0' or cpu_ncs5='1'  then  --or cpu_addr24='1'
    can_ale<='0';
  	 can_wr<='1';
  	 can_rd<='1';
  	 cana_ncs<='1';
	 canb_ncs<='1';
	 can_en_addr<='1';
	 can_en_data<='1';
	 can_dir_data<='1';
	 delay_can<=0;
    can_state<="00";
  elsif sysclk'event and sysclk='0' then
    case can_state is
      when "00" =>
   	can_ale<='1';
		can_en_addr<='0';
		delay_can<=delay_can+1;
		if delay_can=2 then
		  can_ale<='0';
		  cana_ncs<=cpu_addr23;
		  canb_ncs<=not cpu_addr23;
		  delay_can<=0;
		  can_state<="01";
		end if;

	 when "01" =>
	   can_wr<=cpu_nwe;
		can_rd<=cpu_noe;
		can_dir_data<=cpu_noe;
		can_en_addr<='1';
		can_state<="10";
		
	 when "10" =>
		can_en_data<='0';
		delay_can<=delay_can+1;
		if delay_can=3 then
		  can_wr<='1';
		  can_state<="11";
		end if;
	 when "11" =>
            can_state<="11";
	 when others =>
	

    end case;
  end if;
end process;

--cpu write and read
process(can_en_addr,can_en_data,can_dir_data)
begin
  if can_en_addr='0' then
    can_ad<=cpu_addr;
  elsif can_en_data='0' and can_dir_data='1' then
    if cpu_addr(0)='0' then
      can_ad<=cpu_data(7 downto 0);
	 else
	   can_ad<=cpu_data(15 downto 8);    
    end if;
  else
    can_ad<="ZZZZZZZZ";
  end if;
end process;

process(cpu_ncs5,cpu_noe,can_en_data)--can_dir_data
begin
  if can_en_data='0' and can_dir_data='0' then
    cpu_data(7 downto 0)<=can_ad;--"11110000";
	 cpu_data(15 downto 8)<=can_ad;--"00001111";
  else
      cpu_data<="ZZZZZZZZZZZZZZZZ";
  end if;
end process;  


-- cana_ncs<='0';
-- canb_ncs<='0';
 test_led<=led_buf;
 eth_clk<=eth_clk_buf;
 eth_nwe<=cpu_nwe;
 eth_noe<=cpu_noe;
 
 can_dir<=can_dir_data;
 nreset_cpu<=nreset_3828;
 cf_reset  <=nreset_3828;
 speaker   <=not nreset_3828;
 eth_reset <=not nreset_3828;	
 can_nreset<=nreset_3828; 
 		 
end Behavioral;