📄 top.syr
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Release 8.1.03i - xst I.27Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to ./xst/projnav.tmpCPU : 0.00 / 2.45 s | Elapsed : 0.00 / 2.00 s --> Parameter xsthdpdir set to ./xstCPU : 0.00 / 2.45 s | Elapsed : 0.00 / 2.00 s --> Reading design: top.prjTABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Final Report=========================================================================* Synthesis Options Summary *=========================================================================---- Source ParametersInput File Name : "top.prj"Input Format : mixedIgnore Synthesis Constraint File : NO---- Target ParametersOutput File Name : "top"Output Format : NGCTarget Device : XC9500XL CPLDs---- Source OptionsTop Module Name : topAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoMux Extraction : YESResource Sharing : YES---- Target OptionsAdd IO Buffers : YESMACRO Preserve : YESXOR Preserve : YESEquivalent register Removal : YES---- General OptionsOptimization Goal : SpeedOptimization Effort : 1Keep Hierarchy : YESRTL Output : YesHierarchy Separator : /Bus Delimiter : <>Case Specifier : maintain---- Other Optionslso : top.lsoverilog2001 : YESsafe_implementation : Nowysiwyg : NO==================================================================================================================================================* HDL Compilation *=========================================================================Compiling vhdl file "G:/gui_test/pxa255_cpld/topt.vhd" in Library work.Architecture behavioral of Entity top is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <top> (Architecture <behavioral>).WARNING:Xst:819 - "G:/gui_test/pxa255_cpld/topt.vhd" line 101: The following signals are missing in the process sensitivity list: nreset_3828, cpu_ncs5.WARNING:Xst:819 - "G:/gui_test/pxa255_cpld/topt.vhd" line 152: The following signals are missing in the process sensitivity list: cpu_addr, cpu_data.WARNING:Xst:819 - "G:/gui_test/pxa255_cpld/topt.vhd" line 167: The following signals are missing in the process sensitivity list: can_dir_data, can_ad.Entity <top> analyzed. Unit <top> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <top>. Related source file is "G:/gui_test/pxa255_cpld/topt.vhd".WARNING:Xst:647 - Input <cpu_addr24> is never used.WARNING:Xst:647 - Input <cpu_ncs1> is never used.WARNING:Xst:647 - Input <cpu_ncs3> is never used.WARNING:Xst:1306 - Output <cpu_nwait> is never assigned. Register <can_dir_data> equivalent to <can_rd> has been removed Found finite state machine <FSM_0> for signal <can_state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 6 | | Inputs | 2 | | Outputs | 5 | | Clock | sysclk (falling_edge) | | Reset | $n0004 (positive) | | Reset type | asynchronous | | Reset State | 00 | | Encoding | automatic | | Implementation | automatic | ----------------------------------------------------------------------- Found 16-bit tristate buffer for signal <cpu_data>. Found 1-bit register for signal <can_ale>. Found 1-bit register for signal <cana_ncs>. Found 1-bit register for signal <canb_ncs>. Found 1-bit register for signal <can_wr>. Found 1-bit register for signal <can_rd>. Found 8-bit tristate buffer for signal <can_ad>. Found 22-bit comparator greatequal for signal <$n0014> created at line 92. Found 3-bit adder for signal <$n0022> created at line 115. Found 1-bit register for signal <can_en_addr>. Found 1-bit register for signal <can_en_data>. Found 3-bit register for signal <delay_can>. Found 1-bit register for signal <eth_clk_buf>. Found 1-bit register for signal <led_buf>. Found 22-bit up counter for signal <led_count>. Summary: inferred 1 Finite State Machine(s). inferred 1 Counter(s). inferred 9 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Comparator(s). inferred 24 Tristate(s).Unit <top> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 1 3-bit adder : 1# Counters : 1 22-bit up counter : 1# Registers : 10 1-bit register : 9 3-bit register : 1# Comparators : 1 22-bit comparator greatequal : 1# Tristates : 17 1-bit tristate buffer : 16 8-bit tristate buffer : 1==================================================================================================================================================* Advanced HDL Synthesis *=========================================================================Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <can_state[1:2]> with sequential encoding.------------------- State | Encoding------------------- 00 | 00 01 | 01 10 | 10 11 | 11-------------------=========================================================================Advanced HDL Synthesis ReportMacro Statistics# FSMs : 1# Adders/Subtractors : 1 3-bit adder : 1# Counters : 1 22-bit up counter : 1# Registers : 36 Flip-Flops : 36==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <top> ... implementation constraint: INIT=r : led_count_0 implementation constraint: INIT=r : delay_can_2 implementation constraint: INIT=r : delay_can_0 implementation constraint: INIT=r : delay_can_1 implementation constraint: INIT=r : led_count_21 implementation constraint: INIT=r : led_count_20 implementation constraint: INIT=r : led_count_19 implementation constraint: INIT=r : led_count_18 implementation constraint: INIT=r : led_count_17 implementation constraint: INIT=r : led_count_16 implementation constraint: INIT=r : led_count_15 implementation constraint: INIT=r : led_count_14 implementation constraint: INIT=r : led_count_13 implementation constraint: INIT=r : led_count_12 implementation constraint: INIT=r : led_count_11 implementation constraint: INIT=r : led_count_10 implementation constraint: INIT=r : led_count_9 implementation constraint: INIT=r : led_count_8 implementation constraint: INIT=r : led_count_7 implementation constraint: INIT=r : led_count_6 implementation constraint: INIT=r : led_count_5 implementation constraint: INIT=r : led_count_4 implementation constraint: INIT=r : led_count_3 implementation constraint: INIT=r : led_count_2 implementation constraint: INIT=r : led_count_1=========================================================================* Final Report *=========================================================================Final ResultsRTL Top Level Output File Name : top.ngrTop Level Output File Name : topOutput Format : NGCOptimization Goal : SpeedKeep Hierarchy : YESTarget Technology : XC9500XL CPLDsMacro Preserve : YESXOR Preserve : YESwysiwyg : NODesign Statistics# IOs : 57Cell Usage :# BELS : 235# AND2 : 103# AND3 : 3# AND4 : 1# GND : 1# INV : 70# OR2 : 31# OR3 : 2# OR4 : 1# XOR2 : 23# FlipFlops/Latches : 36# FD : 23# FDC : 5# FDCE : 2# FDP : 2# FDPE : 4# IO Buffers : 53# IBUF : 14# IOBUFE : 24# OBUF : 15=========================================================================CPU : 10.28 / 12.80 s | Elapsed : 10.00 / 12.00 s --> Total memory usage is 92692 kilobytesNumber of errors : 0 ( 0 filtered)Number of warnings : 7 ( 0 filtered)Number of infos : 1 ( 0 filtered)⌨️ 快捷键说明
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