usbsoftlock.vhd

< FPGA数字电子系统设计与开发实例导航> 一书的代码

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--
-- File        : e:\Courses\ComputerHardwareInterface\USB_IF_DESIGN\USB_IF\src\USBSoftLock.vhd
-- Create Time : Mon Apr 19 22:36:04 2004
-- Title       : USBSoftLock
-- Design      : USB Interface IP Core
-- Author      : Lou Xinghua ([e-mail])
-- Company     : Department of Engineering Physics in Tsinghua Unversity, Beijing, China
-- Version     : 1.0
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {USBSoftLock} architecture {USBSoftLock}}

library IEEE;				  
use WORK.USB_PACKAGE.all;
use WORK.PDIUSBD12_PACKAGE.all;
use IEEE.STD_LOGIC_1164.all;  



entity USBSoftLock is
	port(
		reset_n : in STD_LOGIC;
		clk : in STD_LOGIC;
		int_n_in : in STD_LOGIC;
		a0 : out STD_LOGIC;	 
		data : inout STD_LOGIC_VECTOR(7 downto 0);
		wr_n : out STD_LOGIC;
		rd_n : out STD_LOGIC;
		ale : out STD_LOGIC;
		cs_n : out STD_LOGIC;
		suspend: inout STD_LOGIC;
		d12_reset_n : out STD_LOGIC;  
		step : out STD_LOGIC_VECTOR(7 downto 0);
		d12_wr : out STD_LOGIC;
		d12_rd : out STD_LOGIC
	);
end USBSoftLock;

--}} End of automatically maintained section

architecture USBSoftLock of USBSoftLock is

-- Signal Declaration
signal clk_div: STD_LOGIC;		-- divided clock
--signal int_n_out: STD_LOGIC;
signal wr_n_ce: STD_LOGIC;
signal rd_n_ce: STD_LOGIC;
signal recv_n: STD_LOGIC;
signal req_type: STD_LOGIC_VECTOR(7 downto 0);
signal cmd: STD_LOGIC_VECTOR(7 downto 0);
signal exec_n: STD_LOGIC;	
signal data_in: STD_LOGIC_VECTOR(7 downto 0); 
signal data_out: STD_LOGIC_VECTOR(7 downto 0);

signal reset_ts: STD_LOGIC;

-- Component Declaration
component FrequencyDivider is 
	generic( 
		div_factor : INTEGER8 := 0
	);
	port(					
		reset_n : in STD_LOGIC;	  
		clk_origin : in STD_LOGIC; 
		clk : out STD_LOGIC
	);
end component;

component EdgeController is
	port(
		clk : in STD_LOGIC;	
		ce_n : in STD_LOGIC;	  
		edge : out STD_LOGIC	);
end component;

--component InterruptDetector is	
--	generic(
--		pulse_width: INTEGER8 := 0
--	);
--	port(						
--	 	reset_n : in STD_LOGIC; 
--	 	clk : in STD_LOGIC;
--	 	int_n_in : in STD_LOGIC;  
--	 	int_n_out : out STD_LOGIC
--	);
--end component;

component DeviceTranseiver is
	port(					  
		 reset_n : in STD_LOGIC; 
		 clk : in STD_LOGIC;  
		 int_n : in STD_LOGIC;	
		 a0 : out STD_LOGIC;						 
		 data_in : inout STD_LOGIC_VECTOR(7 downto 0); 
		 data_out : inout STD_LOGIC_VECTOR(7 downto 0);
		 wr_n : out STD_LOGIC;
		 rd_n : out STD_LOGIC;
		 suspend : inout STD_LOGIC;
		 recv_n : out STD_LOGIC;
		 cmd : in STD_LOGIC_VECTOR(7 downto 0);
		 exec_n: in STD_LOGIC;
		 req_type : out STD_LOGIC_VECTOR(7 downto 0);
		 step : out std_logic_vector(7 downto 0)
	);
end component; 

component RequestHandler is
	port(		   
		reset_n : in STD_LOGIC;		
		clk : in STD_LOGIC;  
		recv_n : in STD_LOGIC;
		req_type : in STD_LOGIC_VECTOR(7 downto 0);  
		cmd : out STD_LOGIC_VECTOR(7 downto 0);
		exec_n : out STD_LOGIC
	);
end component; 

component IOSwitch is
	port( 	
		data : inout STD_LOGIC_VECTOR(7 downto 0);
		din : in STD_LOGIC_VECTOR(7 downto 0);
		dout : out STD_LOGIC_VECTOR(7 downto 0);
		sel_in_n : in STD_LOGIC;
		sel_out_n : in STD_LOGIC
	    );
end component;

begin

	-- enter your statements here --	
	
	-- Signal Connection
	d12_wr <= wr_n_ce;
	d12_rd <= rd_n_ce;
	
--	suspend <= '0';	
	ale <= '0';
	cs_n <= '0'; 
	d12_reset_n <= '1';

	-- Init Device
	process(reset_n, clk_div)
	variable handle_step : INTEGER range 0 to 7 := 0; 
	variable delay_count : INTEGER range 0 to 10000 := 0;
	begin
		if reset_n = '0' then
			handle_step := 0;
			delay_count := 0;
			reset_ts <= '0';
--			d12_reset_n <= '0';
		elsif rising_edge(clk_div) then
			case handle_step is
			when 0 | 1 | 2 => 
				handle_step := handle_step+1;
			when 3 =>
--				d12_reset_n <= '1';
				handle_step := handle_step+1;
			when 4 => 	-- wait for more than 3 ms after D12 reset
				delay_count := delay_count+1;
				if delay_count = RESET_D12_DELAY then
					handle_step := handle_step+1;
				end if;					 
			when 5 =>
				reset_ts <= '1';
				handle_step := handle_step+1;
			when others =>
				null;	
			end case;
		end if;
	end process;
	
	-- Component Connnections
	U_FrequencyDivider : FrequencyDivider
	generic	map(div_factor => CLOCK_DIV_FACTOR)
	port map(reset_n => reset_n, clk_origin => clk, clk => clk_div);   
	
	U_EdgeController_Write : EdgeController
	port map(clk => clk_div, ce_n => wr_n_ce, edge => wr_n);
	
	U_EdgeController_Read : EdgeController
	port map(clk => clk_div, ce_n => rd_n_ce, edge => rd_n);  
	
	U_DeviceTranseiver : DeviceTranseiver
	port map(
		reset_n => reset_ts,
		clk => clk_div,
		int_n => int_n_in,
		a0 => a0,
		data_in => data_in,
		data_out => data_out,
		wr_n => wr_n_ce,
		rd_n => rd_n_ce,
		suspend => suspend,
		recv_n => recv_n,
		req_type => req_type,
		cmd => cmd,
		exec_n => exec_n,
		step => step);
		
	U_IOSwitch : IOSwitch
	port map(
		din => data_out,
		dout => data_in,
		data => data,
		sel_in_n => wr_n_ce,
		sel_out_n => rd_n_ce
	);
		
	U_RequestHandler : RequestHandler
	port map(
		reset_n => reset_ts,
		clk => clk_div,
		recv_n => recv_n,
		req_type => req_type,
		cmd => cmd,
		exec_n => exec_n
	);			
	
end USBSoftLock;