i2c_master_top.syr

< FPGA数字电子系统设计与开发实例导航> 一书的代码

    Found 1-bit register for signal <wb_ack_o>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0003> created at line 158.
    Found 1-bit register for signal <al>.
    Found 8-bit register for signal <cr>.
    Found 8-bit register for signal <ctr>.
    Found 1-bit register for signal <irq_flag>.
    Found 16-bit register for signal <prer>.
    Found 1-bit register for signal <rxack>.
    Found 1-bit register for signal <tip>.
    Found 8-bit register for signal <txr>.
    Summary:
	inferred  54 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <i2c_master_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# Registers                        : 59
  1-bit register                   : 52
  4-bit register                   : 1
  8-bit register                   : 4
  16-bit register                  : 1
  3-bit register                   : 1
# Multiplexers                     : 1
  8-bit 8-to-1 multiplexer         : 1
# Adders/Subtractors               : 2
  16-bit subtractor                : 1
  3-bit subtractor                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <c_state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <c_state> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <i2c_master_top> ...

Optimizing unit <i2c_master_bit_ctrl> ...

Optimizing unit <i2c_master_byte_ctrl> ...
Loading device for application Xst from file '2s50e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c_master_top, actual ratio is 17.
FlipFlop byte_controller_bit_controller_al has been replicated 1 time(s)
FlipFlop wb_ack_o has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : i2c_master_top.ngr
Top Level Output File Name         : i2c_master_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 33

Macro Statistics :
# Registers                        : 59
#      1-bit register              : 52
#      16-bit register             : 1
#      3-bit register              : 1
#      4-bit register              : 1
#      8-bit register              : 4
# Multiplexers                     : 1
#      8-bit 8-to-1 multiplexer    : 1
# Adders/Subtractors               : 1
#      16-bit subtractor           : 1

Cell Usage :
# BELS                             : 300
#      GND                         : 1
#      LUT1                        : 18
#      LUT2                        : 50
#      LUT2_D                      : 1
#      LUT2_L                      : 4
#      LUT3                        : 61
#      LUT3_D                      : 2
#      LUT3_L                      : 1
#      LUT4                        : 89
#      LUT4_D                      : 1
#      LUT4_L                      : 16
#      MUXCY                       : 15
#      MUXF5                       : 16
#      MUXF6                       : 8
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 133
#      FD                          : 9
#      FDC                         : 26
#      FDCE                        : 70
#      FDE                         : 1
#      FDP                         : 6
#      FDPE                        : 19
#      FDR                         : 2
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 32
#      IBUF                        : 18
#      OBUF                        : 14
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                     134  out of    768    17%  
 Number of Slice Flip Flops:           133  out of   1536     8%  
 Number of 4 input LUTs:               243  out of   1536    15%  
 Number of bonded IOBs:                 32  out of    102    31%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
wb_clk_i                           | BUFGP                  | 133   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.441ns (Maximum Frequency: 105.921MHz)
   Minimum input arrival time before clock: 11.700ns
   Maximum output required time after clock: 6.914ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'wb_clk_i'
Delay:               9.441ns (Levels of Logic = 4)
  Source:            byte_controller_bit_controller_cnt_7 (FF)
  Destination:       byte_controller_bit_controller_cnt_5 (FF)
  Source Clock:      wb_clk_i rising
  Destination Clock: wb_clk_i rising

  Data Path: byte_controller_bit_controller_cnt_7 to byte_controller_bit_controller_cnt_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.992   1.150  byte_controller_bit_controller_cnt_7 (byte_controller_bit_controller_cnt_7)
     LUT4:I0->O            1   0.468   0.920  byte_controller_bit_controller__n005349 (CHOICE215)
     LUT2:I0->O            1   0.468   0.920  byte_controller_bit_controller__n005363 (CHOICE223)
     LUT4_D:I2->LO         1   0.468   0.100  byte_controller_bit_controller__n005394 (N9536)
     LUT4:I2->O           16   0.468   2.800  byte_controller_bit_controller__n00651 (byte_controller_bit_controller__n0065)
     FDCE:CE                   0.687          byte_controller_bit_controller_cnt_0
    ----------------------------------------
    Total                      9.441ns (3.551ns logic, 5.890ns route)
                                       (37.6% logic, 62.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'wb_clk_i'
Offset:              11.700ns (Levels of Logic = 4)
  Source:            wb_rst_i (PAD)
  Destination:       byte_controller_bit_controller_c_state_FFd14 (FF)
  Destination Clock: wb_clk_i rising

  Data Path: wb_rst_i to byte_controller_bit_controller_c_state_FFd14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            99   0.797   4.975  wb_rst_i_IBUF (wb_rst_i_IBUF)
     LUT2:I1->O           14   0.468   2.650  byte_controller_Ker67051 (CHOICE167)
     LUT4:I3->O            2   0.468   1.150  byte_controller_bit_controller_Ker58071 (byte_controller_bit_controller_N5809)
     LUT3:I1->O            1   0.468   0.000  byte_controller_bit_controller_c_state_FFd14-In1 (byte_controller_bit_controller_c_state_FFd14-In)
     FDCE:D                    0.724          byte_controller_bit_controller_c_state_FFd14
    ----------------------------------------
    Total                     11.700ns (2.925ns logic, 8.775ns route)
                                       (25.0% logic, 75.0% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'wb_clk_i'
Offset:              6.914ns (Levels of Logic = 1)
  Source:            byte_controller_bit_controller_scl_oen (FF)
  Destination:       scl_padoen_o (PAD)
  Source Clock:      wb_clk_i rising

  Data Path: byte_controller_bit_controller_scl_oen to scl_padoen_o
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDPE:C->Q             3   0.992   1.320  byte_controller_bit_controller_scl_oen (byte_controller_bit_controller_scl_oen)
     OBUF:I->O                 4.602          scl_padoen_o_OBUF (scl_padoen_o)
    ----------------------------------------
    Total                      6.914ns (5.594ns logic, 1.320ns route)
                                       (80.9% logic, 19.1% route)

=========================================================================
CPU : 5.25 / 5.76 s | Elapsed : 5.00 / 6.00 s
 
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Total memory usage is 59788 kilobytes