i2c_master_top.syr

< FPGA数字电子系统设计与开发实例导航> 一书的代码

Release 6.1i - xst G.23
Copyright (c) 1995-2003 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.24 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.24 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: i2c_master_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
     4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : i2c_master_top.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : i2c_master_top
Output Format                      : NGC
Target Device                      : xc2s50e-6-tq144

---- Source Options
Top Module Name                    : i2c_master_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : i2c_master_top.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO

=========================================================================

WARNING:Xst:1885 - LSO file is empty, default list of libraries is used

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "i2c_master_bit_ctrl.v"
Compiling include file "i2c_master_defines.v"
Module <i2c_master_bit_ctrl> compiled
Compiling source file "i2c_master_byte_ctrl.v"
Compiling include file "i2c_master_defines.v"
WARNING:HDLCompilers:38 - i2c_master_defines.v line 60 Macro 'I2C_CMD_NOP' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 61 Macro 'I2C_CMD_START' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 62 Macro 'I2C_CMD_STOP' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 63 Macro 'I2C_CMD_WRITE' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 64 Macro 'I2C_CMD_READ' redefined
Module <i2c_master_byte_ctrl> compiled
Compiling source file "i2c_master_top.v"
Compiling include file "i2c_master_defines.v"
WARNING:HDLCompilers:38 - i2c_master_defines.v line 60 Macro 'I2C_CMD_NOP' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 61 Macro 'I2C_CMD_START' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 62 Macro 'I2C_CMD_STOP' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 63 Macro 'I2C_CMD_WRITE' redefined
WARNING:HDLCompilers:38 - i2c_master_defines.v line 64 Macro 'I2C_CMD_READ' redefined
Module <i2c_master_top> compiled
No errors in compilation
Analysis of file <i2c_master_top.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <i2c_master_top>.
WARNING:Xst:916 - i2c_master_top.v line 153: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_top.v line 174: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_top.v line 175: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_top.v line 176: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_top.v line 180: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <i2c_master_top> is correct for synthesis.
 
Analyzing module <i2c_master_byte_ctrl>.
WARNING:Xst:916 - i2c_master_byte_ctrl.v line 168: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_byte_ctrl.v line 170: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_byte_ctrl.v line 172: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_byte_ctrl.v line 174: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_byte_ctrl.v line 179: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <i2c_master_byte_ctrl> is correct for synthesis.
 
Analyzing module <i2c_master_bit_ctrl>.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 180: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 189: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 190: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 194: Delay is ignored for synthesis.
WARNING:Xst:916 - i2c_master_bit_ctrl.v line 195: Delay is ignored for synthesis.
WARNING:Xst:915 - Message (916) is reported only 5 times for each module.
Module <i2c_master_bit_ctrl> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <i2c_master_bit_ctrl>.
    Related source file is i2c_master_bit_ctrl.v.
    Found finite state machine <FSM_0> for signal <c_state>.
    -----------------------------------------------------------------------
    | States             | 18                                             |
    | Transitions        | 50                                             |
    | Inputs             | 6                                              |
    | Outputs            | 19                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0001 (positive)                              |
    | Reset              | nReset (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000000000000000001                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <sda_oen>.
    Found 1-bit register for signal <al>.
    Found 1-bit register for signal <cmd_ack>.
    Found 1-bit register for signal <busy>.
    Found 1-bit register for signal <scl_oen>.
    Found 1-bit register for signal <dout>.
    Found 16-bit subtractor for signal <$n0049> created at line 210.
    Found 1-bit register for signal <clk_en>.
    Found 1-bit register for signal <cmd_stop>.
    Found 16-bit register for signal <cnt>.
    Found 1-bit register for signal <dcmd_stop>.
    Found 1-bit register for signal <dSCL>.
    Found 1-bit register for signal <dscl_oen>.
    Found 1-bit register for signal <dSDA>.
    Found 1-bit register for signal <sda_chk>.
    Found 1-bit register for signal <sSCL>.
    Found 1-bit register for signal <sSDA>.
    Found 1-bit register for signal <sta_condition>.
    Found 1-bit register for signal <sto_condition>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <i2c_master_bit_ctrl> synthesized.


Synthesizing Unit <i2c_master_byte_ctrl>.
    Related source file is i2c_master_byte_ctrl.v.
    Found finite state machine <FSM_1> for signal <c_state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 31                                             |
    | Inputs             | 9                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | nReset (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000001                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <cmd_ack>.
    Found 1-bit register for signal <ack_out>.
    Found 3-bit subtractor for signal <$n0021> created at line 185.
    Found 4-bit register for signal <core_cmd>.
    Found 1-bit register for signal <core_txd>.
    Found 3-bit register for signal <dcnt>.
    Found 1-bit register for signal <ld>.
    Found 1-bit register for signal <shift>.
    Found 8-bit register for signal <sr>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  20 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <i2c_master_byte_ctrl> synthesized.


Synthesizing Unit <i2c_master_top>.
    Related source file is i2c_master_top.v.
    Found 8-bit register for signal <wb_dat_o>.
    Found 1-bit register for signal <wb_inta_o>.