i2c_master_byte_ctrl.syr

< FPGA数字电子系统设计与开发实例导航> 一书的代码

	inferred   1 Adder/Subtracter(s).
Unit <i2c_master_byte_ctrl> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 2
# Registers                        : 26
  1-bit register                   : 22
  4-bit register                   : 1
  16-bit register                  : 1
  8-bit register                   : 1
  3-bit register                   : 1
# Adders/Subtractors               : 2
  16-bit subtractor                : 1
  3-bit subtractor                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <c_state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <c_state> with one-hot encoding.

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <i2c_master_byte_ctrl> ...

Optimizing unit <i2c_master_bit_ctrl> ...
Loading device for application Xst from file '2s50e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c_master_byte_ctrl, actual ratio is 12.
FlipFlop bit_controller_al has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : i2c_master_byte_ctrl.ngr
Top Level Output File Name         : i2c_master_byte_ctrl
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 51

Macro Statistics :
# Registers                        : 26
#      1-bit register              : 22
#      16-bit register             : 1
#      3-bit register              : 1
#      4-bit register              : 1
#      8-bit register              : 1
# Adders/Subtractors               : 1
#      16-bit subtractor           : 1

Cell Usage :
# BELS                             : 202
#      GND                         : 1
#      LUT1                        : 17
#      LUT2                        : 20
#      LUT2_L                      : 2
#      LUT3                        : 31
#      LUT3_D                      : 1
#      LUT4                        : 82
#      LUT4_D                      : 1
#      LUT4_L                      : 15
#      MUXCY                       : 15
#      VCC                         : 1
#      XORCY                       : 16
# FlipFlops/Latches                : 78
#      FD                          : 1
#      FDC                         : 21
#      FDCE                        : 46
#      FDE                         : 1
#      FDP                         : 6
#      FDPE                        : 3
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 50
#      IBUF                        : 34
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50etq144-6 

 Number of Slices:                      95  out of    768    12%  
 Number of Slice Flip Flops:            78  out of   1536     5%  
 Number of 4 input LUTs:               169  out of   1536    11%  
 Number of bonded IOBs:                 50  out of    102    49%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 78    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 11.421ns (Maximum Frequency: 87.558MHz)
   Minimum input arrival time before clock: 10.925ns
   Maximum output required time after clock: 8.694ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               11.421ns (Levels of Logic = 4)
  Source:            bit_controller_cnt_7 (FF)
  Destination:       bit_controller_cnt_8 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: bit_controller_cnt_7 to bit_controller_cnt_8
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             2   0.992   1.150  bit_controller_cnt_7 (bit_controller_cnt_7)
     LUT4:I0->O            1   0.468   0.920  bit_controller__n005349 (CHOICE209)
     LUT2_L:I0->LO         1   0.468   0.100  bit_controller__n005363 (CHOICE217)
     LUT4:I2->O           18   0.468   2.900  bit_controller__n005394 (bit_controller__n0053)
     LUT4:I2->O           16   0.468   2.800  bit_controller__n00651 (bit_controller__n0065)
     FDCE:CE                   0.687          bit_controller_cnt_0
    ----------------------------------------
    Total                     11.421ns (3.551ns logic, 7.870ns route)
                                       (31.1% logic, 68.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              10.925ns (Levels of Logic = 4)
  Source:            rst (PAD)
  Destination:       bit_controller_c_state_FFd14 (FF)
  Destination Clock: clk rising

  Data Path: rst to bit_controller_c_state_FFd14
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            64   0.797   4.100  rst_IBUF (rst_IBUF)
     LUT2:I1->O           15   0.468   2.750  Ker38031 (CHOICE161)
     LUT4:I3->O            2   0.468   1.150  bit_controller_Ker50691 (bit_controller_N5071)
     LUT3:I1->O            1   0.468   0.000  bit_controller_c_state_FFd14-In1 (bit_controller_c_state_FFd14-In)
     FDCE:D                    0.724          bit_controller_c_state_FFd14
    ----------------------------------------
    Total                     10.925ns (2.925ns logic, 8.000ns route)
                                       (26.8% logic, 73.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              8.694ns (Levels of Logic = 1)
  Source:            bit_controller_al_1 (FF)
  Destination:       i2c_al (PAD)
  Source Clock:      clk rising

  Data Path: bit_controller_al_1 to i2c_al
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             24   0.992   3.100  bit_controller_al_1 (bit_controller_al_1)
     OBUF:I->O                 4.602          i2c_al_OBUF (i2c_al)
    ----------------------------------------
    Total                      8.694ns (5.594ns logic, 3.100ns route)
                                       (64.3% logic, 35.7% route)

=========================================================================
CPU : 4.44 / 5.00 s | Elapsed : 5.00 / 5.00 s
 
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Total memory usage is 58764 kilobytes