detector_tb.vhd

< FPGA数字电子系统设计与开发实例导航> 一书的代码

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--
-- Title       : Test Bench for detector
-- Design      : UART
-- Author      : Xinghua Lou
-- Company     : Tsinghua University
--
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--
-- File        : $DSN\src\TestBench\detector_TB.vhd
-- Generated   : 4/12/2005, 3:41 PM
-- From        : $DSN\src\detector.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
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--
-- Description : Automatically generated Test Bench for detector_tb
--
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library ieee;
use work.uart_package.all;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity detector_tb is
end detector_tb;

architecture TB_ARCHITECTURE of detector_tb is
	-- Component declaration of the tested unit
	component detector
	port(
		clk : in std_logic;
		reset_n : in std_logic;
		RxD : in std_logic;
		new_data : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clk : std_logic := '0';
	signal reset_n : std_logic;
	signal RxD : std_logic;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal new_data : std_logic;

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : detector
		port map (
			clk => clk,
			reset_n => reset_n,
			RxD => RxD,
			new_data => new_data
		);

	-- Add your stimulus here ...	
	
	-- 产生时钟信号
	clk_gen : process
	begin
		clk <= not clk;
		wait for 50 ns;
	end process;

	-- 测试主流程
	main: process
	begin
		reset_n <= '0';
		RxD <= '1';	
		wait for 200 ns;
		reset_n <= '1';
		wait for 250 ns;
		RxD <= '0';
		wait for 100 ns;
		RxD <= '1';
		wait for 100 ns;
		RxD <= '0';
		wait for 200 ns;
		reset_n <= '0';
		RxD <= '1';
		wait for 100 ns;
		reset_n <= '1';
		RxD <= '0';
		wait for 100 ns;
		RxD <= '1';
		
		wait;
		
	end process;
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_detector of detector_tb is
	for TB_ARCHITECTURE
		for UUT : detector
			use entity work.detector(detector);
		end for;
	end for;
end TESTBENCH_FOR_detector;