switch_bus_tb.vhd

< FPGA数字电子系统设计与开发实例导航> 一书的代码

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--
-- Title       : Test Bench for switch_bus
-- Design      : UART
-- Author      : Xinghua Lou
-- Company     : Tsinghua University
--
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--
-- File        : $DSN\src\TestBench\switch_bus_TB.vhd
-- Generated   : 4/12/2005, 4:07 PM
-- From        : $DSN\src\switch_bus.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
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--
-- Description : Automatically generated Test Bench for switch_bus_tb
--
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library ieee;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity switch_bus_tb is
	-- Generic declarations of the tested unit
		generic(
		BUS_WIDTH : INTEGER := 8 );
end switch_bus_tb;

architecture TB_ARCHITECTURE of switch_bus_tb is
	-- Component declaration of the tested unit
	component switch_bus
		generic(
		BUS_WIDTH : INTEGER := 8 );
	port(
		din1 : in std_logic_vector((BUS_WIDTH-1) downto 0);
		din2 : in std_logic_vector((BUS_WIDTH-1) downto 0);
		sel : in std_logic;
		dout : out std_logic_vector((BUS_WIDTH-1) downto 0) );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal din1 : std_logic_vector((BUS_WIDTH-1) downto 0);
	signal din2 : std_logic_vector((BUS_WIDTH-1) downto 0);
	signal sel : std_logic;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal dout : std_logic_vector((BUS_WIDTH-1) downto 0);

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : switch_bus
		generic map (
			BUS_WIDTH => BUS_WIDTH
		)

		port map (
			din1 => din1,
			din2 => din2,
			sel => sel,
			dout => dout
		);

	-- Add your stimulus here ... 
	main: process
	begin
		din1 <= "11110000";
		din2 <= "00001111";
		sel <= '0';
		wait for 100 ns;
		sel <= '1';
		wait;	 
	end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_switch_bus of switch_bus_tb is
	for TB_ARCHITECTURE
		for UUT : switch_bus
			use entity work.switch_bus(switch_bus);
		end for;
	end for;
end TESTBENCH_FOR_switch_bus;