shift_register_tb.vhd

< FPGA数字电子系统设计与开发实例导航> 一书的代码

---------------------------------------------------------------------------------------------------
--
-- Title       : Test Bench for shift_register
-- Design      : UART
-- Author      : Xinghua Lou
-- Company     : Tsinghua University
--
---------------------------------------------------------------------------------------------------
--
-- File        : $DSN\src\TestBench\shift_register_TB.vhd
-- Generated   : 4/12/2005, 3:55 PM
-- From        : $DSN\src\shift_register.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
---------------------------------------------------------------------------------------------------
--
-- Description : Automatically generated Test Bench for shift_register_tb
--
---------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity shift_register_tb is
	-- Generic declarations of the tested unit
		generic(
		TOTAL_BIT : INTEGER := 10 );
end shift_register_tb;

architecture TB_ARCHITECTURE of shift_register_tb is
	-- Component declaration of the tested unit
	component shift_register
		generic(
		TOTAL_BIT : INTEGER := 10 );
	port(
		clk : in std_logic;
		reset_n : in std_logic;
		din : in std_logic;
		regs : out std_logic_vector((TOTAL_BIT-1) downto 0);
		dout : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clk : std_logic := '1';
	signal reset_n : std_logic;
	signal din : std_logic := '0';
	-- Observed signals - signals mapped to the output ports of tested entity
	signal regs : std_logic_vector((TOTAL_BIT-1) downto 0) := (others => '0');
	signal dout : std_logic;

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : shift_register
		generic map (
			TOTAL_BIT => TOTAL_BIT
		)

		port map (
			clk => clk,
			reset_n => reset_n,
			din => din,
			regs => regs,
			dout => dout
		);

	-- Add your stimulus here ...	 
	
	-- 产生时钟信号
	clk_gen : process
	begin
		clk <= not clk;
		wait for 50 ns;
	end process;	  
	
	din_gen : process
	begin
		din <= not din;
		wait for 100 ns;
	end process;		
	
	main: process
	begin
		reset_n <= '0';
		wait for 100 ns;
		reset_n <= '1';
		wait;
	end process;
	
end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_shift_register of shift_register_tb is
	for TB_ARCHITECTURE
		for UUT : shift_register
			use entity work.shift_register(shift_register);
		end for;
	end for;
end TESTBENCH_FOR_shift_register;