tb_ethernet.v

< FPGA数字电子系统设计与开发实例导航> 一书的代码

//    test_mii(0, 17);                        // 0 - 17
  test_note("PHY generates ideal Carrier sense and Collision signals for following tests");
  eth_phy.carrier_sense_real_delay(0);
    test_mac_full_duplex_transmit(0, 21);    // 0 - (21)
    test_mac_full_duplex_receive(0, 13);     // 0 - 13
    test_mac_full_duplex_flow_control(0, 4);  // 0 - 4
                                              // 4 is executed, everything is OK
//    test_mac_half_duplex_flow(0, 0);

  test_note("PHY generates 'real delayed' Carrier sense and Collision signals for following tests");
  eth_phy.carrier_sense_real_delay(1);


  // Finish test's logs
  test_summary;
  $display("\n\n END of SIMULATION");
  $fclose(tb_log_file | phy_log_file_desc | memory_log_file_desc | host_log_file_desc);
  $fclose(wb_s_mon_log_file_desc | wb_m_mon_log_file_desc);

  $stop;
end
  


//////////////////////////////////////////////////////////////
// Test tasks
//////////////////////////////////////////////////////////////

task test_access_to_mac_reg;
  input  [31:0]  start_task;
  input  [31:0]  end_task;
  integer        bit_start_1;
  integer        bit_end_1;
  integer        bit_start_2;
  integer        bit_end_2;
  integer        num_of_reg;
  integer        i_addr;
  integer        i_data;
  integer        i_length;
  integer        tmp_data;
  reg    [31:0]  tx_bd_num;
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_data;
  reg    [((`MAX_BLK_SIZE * 32) - 1):0] burst_tmp_data;
  integer        i;
  integer        i1;
  integer        i2;
  integer        i3;
  integer        fail;
  integer        test_num;
  reg    [31:0]  addr;
  reg    [31:0]  data;
  reg    [31:0]  data_max;
begin
// ACCESS TO MAC REGISTERS TEST
test_heading("ACCESS TO MAC REGISTERS TEST");
$display(" ");
$display("ACCESS TO MAC REGISTERS TEST");
fail = 0;

// reset MAC registers
hard_reset;
// reset MAC and MII LOGIC with soft reset
//reset_mac;
//reset_mii;


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  test_access_to_mac_reg:                                     ////
////                                                              ////
////  0: Walking 1 with single cycles across MAC regs.            ////
////  1: Walking 1 with single cycles across MAC buffer descript. ////
////  2: Test max reg. values and reg. values after writing       ////
////     inverse reset values and hard reset of the MAC           ////
////  3: Test buffer desc. RAM preserving values after hard reset ////
////     of the MAC and resetting the logic                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
for (test_num = start_task; test_num <= end_task; test_num = test_num + 1)
begin

  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////  Walking 1 with single cycles across MAC regs.             ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 0) // Walking 1 with single cycles across MAC regs.
  begin
    // TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )
    test_name   = "TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )";
    `TIME; $display("  TEST 0: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC REGISTERS ( VARIOUS BUS DELAYS )");
    
    data = 0;
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
      begin
        wbm_init_waits = i;
        wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
        for (i_addr = 0; i_addr <= 32'h4C; i_addr = i_addr + 4) // register address
          begin
            addr = `ETH_BASE + i_addr;
            // set ranges of R/W bits
            case (addr)
              `ETH_MODER:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 16;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_INT: // READONLY - tested within INT test
                begin
                  bit_start_1 = 32; // not used
                  bit_end_1   = 32; // not used
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_INT_MASK:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 6;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_IPGT:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 6;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_IPGR1:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 6;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_IPGR2:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 6;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_PACKETLEN:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 31;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_COLLCONF:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 5;
                  bit_start_2 = 16; 
                  bit_end_2   = 19; 
                end
              `ETH_TX_BD_NUM: 
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 7;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_CTRLMODER:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 2;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_MIIMODER:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 9;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_MIICOMMAND: // "WRITEONLY" - tested within MIIM test - 3 LSBits are not written here!!!
                begin
                  bit_start_1 = 32; // not used
                  bit_end_1   = 32; // not used
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_MIIADDRESS:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 4;
                  bit_start_2 = 8; 
                  bit_end_2   = 12;
                end
              `ETH_MIITX_DATA:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 15;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_MIIRX_DATA: // READONLY - tested within MIIM test
                begin
                  bit_start_1 = 32; // not used
                  bit_end_1   = 32; // not used
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_MIISTATUS: // READONLY - tested within MIIM test
                begin
                  bit_start_1 = 32; // not used
                  bit_end_1   = 32; // not used
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_MAC_ADDR0:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 31;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                  end
              `ETH_MAC_ADDR1:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 15;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              `ETH_HASH_ADDR0:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 31;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
              default: // `ETH_HASH_ADDR1:
                begin
                  bit_start_1 = 0;
                  bit_end_1   = 31;
                  bit_start_2 = 32; // not used
                  bit_end_2   = 32; // not used
                end
            endcase
            
            for (i_data = 0; i_data <= 31; i_data = i_data + 1) // the position of walking one
              begin
                data = 1'b1 << i_data;
                if ( (addr == `ETH_MIICOMMAND) && (i_data <= 2) ) // DO NOT WRITE to 3 LSBits of MIICOMMAND !!!
                  ;
                else
                  begin
                    wbm_write(addr, data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
                    wait (wbm_working == 0);
                    wbm_read(addr, tmp_data, 4'hF, 1, wbm_init_waits, wbm_subseq_waits);
                    if ( ((i_data >= bit_start_1) && (i_data <= bit_end_1)) ||
                         ((i_data >= bit_start_2) && (i_data <= bit_end_2)) ) // data should be equal to tmp_data
                      begin
                        if (tmp_data !== data)
                        begin
                          fail = fail + 1;
                          test_fail("RW bit of the MAC register was not written or not read");
                          `TIME;
                          $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h", 
                                    wbm_init_waits, addr, data, tmp_data);
                        end
                      end
                    else // data should not be equal to tmp_data
                      begin
                        if (tmp_data === data)
                          begin
                            fail = fail + 1;
                            test_fail("NON RW bit of the MAC register was written, but it shouldn't be");
                            `TIME;
                            $display("wbm_init_waits %d, addr %h, data %h, tmp_data %h",
                                      wbm_init_waits, addr, data, tmp_data);
                          end
                      end
                  end
              end
          end
      end
    // INTERMEDIATE DISPLAYS (The only one)
    $display("    ->buffer descriptors tested with 0, 1, 2, 3 and 4 bus delay cycles");
    if(fail == 0)
      test_ok;
    else
      fail = 0;    // Errors were reported previously
  end
        
        
  ////////////////////////////////////////////////////////////////////
  ////                                                            ////
  ////  Walking 1 with single cycles across MAC buffer descript.  ////
  ////                                                            ////
  ////////////////////////////////////////////////////////////////////
  if (test_num == 1) // Start Walking 1 with single cycles across MAC buffer descript.
  begin
    // TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )
    test_name   = "TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )";
    `TIME; $display("  TEST 1: 'WALKING ONE' WITH SINGLE CYCLES ACROSS MAC BUFFER DESC. ( VARIOUS BUS DELAYS )");
        
    data = 0;
    // set TX and RX buffer descriptors
    tx_bd_num = 32'h40;
    wbm_write(`ETH_TX_BD_NUM, tx_bd_num, 4'hF, 1, 0, 0);
    for (i = 0; i <= 4; i = i + 1) // for initial wait cycles on WB bus
    begin
      wbm_init_waits = i;
      wbm_subseq_waits = {$random} % 5; // it is not important for single accesses
      for (i_addr = 32'h400; i_addr <= 32'h7FC; i_addr = i_addr + 4) // buffer descriptor address
      begin
        addr = `ETH_BASE + i_addr;
        if (i_addr < (32'h400 + (tx_bd_num << 3))) // TX buffer descriptors
        begin
          // set ranges of R/W bits
          case (addr[3])
            1'b0: // buffer control bits
            begin
              bit_start_1 = 0;
              bit_end_1   = 31; // 8;
              bit_start_2 = 11;
              bit_end_2   = 31;
            end
            default: // 1'b1: // buffer pointer
            begin
              bit_start_1 = 0;
              bit_end_1   = 31;
              bit_start_2 = 32; // not used
              bit_end_2   = 32; // not used
            end
          endcase
        end
        else // RX buffer descriptors
        begin
          // set ranges of R/W bits
          case (addr[3])
            1'b0: // buffer control bits
            begin
              bit_start_1 = 0;
              bit_end_1   = 31; // 7;
              bit_start_2 = 13;
              bit_end_2   = 31;
            end
            default: // 1'b1: // buffer pointer
            begin
              bit_start_1 = 0;
              bit_end_1   = 31;
              bit_start_2 = 32; // not used