i2c.map.qmsg

verilog 编写的I2c协议程序

{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(377) " "Info: Verilog HDL Case Statement information at i2c.v(377): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 377 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(456) " "Warning: Verilog HDL assignment warning at i2c.v(456): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 456 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(462) " "Warning: Verilog HDL assignment warning at i2c.v(462): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 462 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(468) " "Warning: Verilog HDL assignment warning at i2c.v(468): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 468 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(474) " "Warning: Verilog HDL assignment warning at i2c.v(474): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 474 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(480) " "Warning: Verilog HDL assignment warning at i2c.v(480): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 480 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(486) " "Warning: Verilog HDL assignment warning at i2c.v(486): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 486 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(492) " "Warning: Verilog HDL assignment warning at i2c.v(492): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 492 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(498) " "Warning: Verilog HDL assignment warning at i2c.v(498): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 498 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(509) " "Warning: Verilog HDL assignment warning at i2c.v(509): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 509 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(510) " "Warning: Verilog HDL assignment warning at i2c.v(510): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 510 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(453) " "Warning: (10270) Verilog HDL statement warning at i2c.v(453): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 453 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(453) " "Info: Verilog HDL Case Statement information at i2c.v(453): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 453 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(521) " "Warning: Verilog HDL assignment warning at i2c.v(521): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 521 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(522) " "Warning: Verilog HDL assignment warning at i2c.v(522): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 522 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(526) " "Warning: Verilog HDL assignment warning at i2c.v(526): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 526 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(527) " "Warning: Verilog HDL assignment warning at i2c.v(527): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 527 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(532) " "Warning: Verilog HDL assignment warning at i2c.v(532): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 532 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(533) " "Warning: Verilog HDL assignment warning at i2c.v(533): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 533 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(538) " "Warning: Verilog HDL assignment warning at i2c.v(538): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 538 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(539) " "Warning: Verilog HDL assignment warning at i2c.v(539): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 539 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(544) " "Warning: Verilog HDL assignment warning at i2c.v(544): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 544 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(545) " "Warning: Verilog HDL assignment warning at i2c.v(545): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 545 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(550) " "Warning: Verilog HDL assignment warning at i2c.v(550): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 550 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(551) " "Warning: Verilog HDL assignment warning at i2c.v(551): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 551 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(556) " "Warning: Verilog HDL assignment warning at i2c.v(556): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 556 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(557) " "Warning: Verilog HDL assignment warning at i2c.v(557): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 557 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(562) " "Warning: Verilog HDL assignment warning at i2c.v(562): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 562 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(563) " "Warning: Verilog HDL assignment warning at i2c.v(563): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 563 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(568) " "Warning: Verilog HDL assignment warning at i2c.v(568): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 568 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(569) " "Warning: Verilog HDL assignment warning at i2c.v(569): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 569 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(574) " "Warning: Verilog HDL assignment warning at i2c.v(574): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 574 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(585) " "Warning: Verilog HDL assignment warning at i2c.v(585): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 585 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(518) " "Warning: (10270) Verilog HDL statement warning at i2c.v(518): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 518 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(518) " "Info: Verilog HDL Case Statement information at i2c.v(518): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 518 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(676) " "Warning: Verilog HDL assignment warning at i2c.v(676): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 676 0 0 } }  } 0}