i2c.map.qmsg

verilog 编写的I2c协议程序

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(305) " "Warning: Verilog HDL assignment warning at i2c.v(305): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 305 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(311) " "Warning: Verilog HDL assignment warning at i2c.v(311): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 311 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(317) " "Warning: Verilog HDL assignment warning at i2c.v(317): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 317 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(323) " "Warning: Verilog HDL assignment warning at i2c.v(323): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 323 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(329) " "Warning: Verilog HDL assignment warning at i2c.v(329): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 329 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(335) " "Warning: Verilog HDL assignment warning at i2c.v(335): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 335 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(341) " "Warning: Verilog HDL assignment warning at i2c.v(341): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 341 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(352) " "Warning: Verilog HDL assignment warning at i2c.v(352): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 352 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(353) " "Warning: Verilog HDL assignment warning at i2c.v(353): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 353 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(359) " "Warning: Verilog HDL assignment warning at i2c.v(359): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 359 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(296) " "Warning: (10270) Verilog HDL statement warning at i2c.v(296): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 296 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(296) " "Info: Verilog HDL Case Statement information at i2c.v(296): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 296 0 0 } }  } 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "i2c.v(153) " "Info: Verilog HDL Case Statement information at i2c.v(153): all case item expressions in this Case Statement are onehot; consider adding a full_case attribute to reduce the logic required to implement this Case Statement" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 153 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(371) " "Warning: Verilog HDL assignment warning at i2c.v(371): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 371 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(373) " "Warning: Verilog HDL assignment warning at i2c.v(373): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 373 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(380) " "Warning: Verilog HDL assignment warning at i2c.v(380): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 380 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(381) " "Warning: Verilog HDL assignment warning at i2c.v(381): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 381 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(385) " "Warning: Verilog HDL assignment warning at i2c.v(385): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 385 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(386) " "Warning: Verilog HDL assignment warning at i2c.v(386): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 386 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(391) " "Warning: Verilog HDL assignment warning at i2c.v(391): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 391 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(392) " "Warning: Verilog HDL assignment warning at i2c.v(392): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 392 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(397) " "Warning: Verilog HDL assignment warning at i2c.v(397): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 397 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(398) " "Warning: Verilog HDL assignment warning at i2c.v(398): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 398 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(403) " "Warning: Verilog HDL assignment warning at i2c.v(403): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 403 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(404) " "Warning: Verilog HDL assignment warning at i2c.v(404): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 404 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(409) " "Warning: Verilog HDL assignment warning at i2c.v(409): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 409 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(410) " "Warning: Verilog HDL assignment warning at i2c.v(410): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 410 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(415) " "Warning: Verilog HDL assignment warning at i2c.v(415): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 415 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(416) " "Warning: Verilog HDL assignment warning at i2c.v(416): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 416 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(421) " "Warning: Verilog HDL assignment warning at i2c.v(421): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 421 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(422) " "Warning: Verilog HDL assignment warning at i2c.v(422): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 422 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(427) " "Warning: Verilog HDL assignment warning at i2c.v(427): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 427 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(428) " "Warning: Verilog HDL assignment warning at i2c.v(428): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 428 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(433) " "Warning: Verilog HDL assignment warning at i2c.v(433): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 433 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(444) " "Warning: Verilog HDL assignment warning at i2c.v(444): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 444 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "i2c.v(377) " "Warning: (10270) Verilog HDL statement warning at i2c.v(377): incomplete Case Statement has no default case item" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 377 0 0 } }  } 0}