armperip.xml

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  GROUP(NAME="Overflowed")
  {
  SEPARATOR(GUINAME="Clock"),
  FIELD[10] (NAME="Clock overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW"),
  SEPARATOR(GUINAME="Event 0"),
  FIELD[8] (NAME="Event 0 overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW"),
  SEPARATOR(GUINAME="Event 1"),
  FIELD[9] (NAME="Event 1 overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW")
  },
  SEPARATOR(TEXTNAME=", Interrupt:", GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE"),
  GROUP(NAME="Interrupt enable")
  {
  SEPARATOR(GUINAME="Clock"),
  FIELD[6] (NAME="Clock interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW"),
  SEPARATOR(GUINAME="Event 0"),
  FIELD[4] (NAME="Event 0 interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW"),
  SEPARATOR(GUINAME="Event 1"),
  FIELD[5] (NAME="Event 1 interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW")
  },
  SEPARATOR(GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE")
}

  </definition>
</displaytype>

<displaytype>
  <name>XScale_CPAccess</name>
  <requires></requires>
  <definition>

TYPEDEF tXScale_CPAccess13 ENUM(WIDTH=1)
{
"" = 0,
"CP13 " = 1
}

TYPEDEF tXScale_CPAccess12 ENUM(WIDTH=1)
{
"" = 0,
"CP12 " = 1
}

TYPEDEF tXScale_CPAccess11 ENUM(WIDTH=1)
{
"" = 0,
"CP11 " = 1
}

TYPEDEF tXScale_CPAccess10 ENUM(WIDTH=1)
{
"" = 0,
"CP10 " = 1
}

TYPEDEF tXScale_CPAccess9 ENUM(WIDTH=1)
{
"" = 0,
"CP9 " = 1
}

TYPEDEF tXScale_CPAccess8 ENUM(WIDTH=1)
{
"" = 0,
"CP8 " = 1
}

TYPEDEF tXScale_CPAccess7 ENUM(WIDTH=1)
{
"" = 0,
"CP7 " = 1
}

TYPEDEF tXScale_CPAccess6 ENUM(WIDTH=1)
{
"" = 0,
"CP6 " = 1
}

TYPEDEF tXScale_CPAccess5 ENUM(WIDTH=1)
{
"" = 0,
"CP5 " = 1
}

TYPEDEF tXScale_CPAccess4 ENUM(WIDTH=1)
{
"" = 0,
"CP4 " = 1
}

TYPEDEF tXScale_CPAccess3 ENUM(WIDTH=1)
{
"" = 0,
"CP3 " = 1
}

TYPEDEF tXScale_CPAccess2 ENUM(WIDTH=1)
{
"" = 0,
"CP2 " = 1
}

TYPEDEF tXScale_CPAccess1 ENUM(WIDTH=1)
{
"" = 0,
"CP1 " = 1
}

TYPEDEF tXScale_CPAccess0 ENUM(WIDTH=1)
{
"" = 0,
"CP0 " = 1
}

TYPEDEF XScale_CPAccess(NAME="Coprocessor Access", CLASS="System") COMPOSITE(WIDTH=32)
{
  FIELD[31:14] (NAME="", TYPE=RESERVED(WIDTH=18), ACCESS="0"),
  SEPARATOR(TEXTNAME="Access to: "),
  FIELD[13] (NAME="Coprocessor 13", TYPE=tXScale_CPAccess13),
  FIELD[12:8] (NAME="", TYPE=RESERVED(WIDTH=5), ACCESS="V"),
  FIELD[7] (NAME="Coprocessor 7", TYPE=tXScale_CPAccess7),
  FIELD[6] (NAME="Coprocessor 6", TYPE=tXScale_CPAccess6),
  FIELD[5:1] (NAME="", TYPE=RESERVED(WIDTH=5), ACCESS="V"),
  FIELD[0] (NAME="Accumulators", TYPE=tXScale_CPAccess0)
}
  </definition>
</displaytype>

<displaytype>
  <name>XScale_INTCTL</name>
  <requires></requires>
  <definition>
TYPEDEF XScale_INTCTL(NAME="Interrupt Control (XScale)", CLASS="System") COMPOSITE(WIDTH=32)
{
  FIELD[31:4] (NAME="", TYPE=RESERVED(WIDTH=28), ACCESS="0"),
  FIELD[3] (NAME="BCU Enable", TYPE=FLAG(SET="B", UNSET="b")),
  FIELD[2] (NAME="PMU Enable", TYPE=FLAG(SET="P", UNSET="p")),
  FIELD[1] (NAME="IRQ Enable", TYPE=FLAG(SET="I", UNSET="i")),
  FIELD[0] (NAME="FIQ Enable", TYPE=FLAG(SET="F", UNSET="f"))
}
  </definition>
</displaytype>

<displaytype>
  <name>ARM1136_PMC</name>
  <requires></requires>
  <definition>
TYPEDEF ARM1136_EventType ENUM(WIDTH=8, DEFAULT="Reserved/unpredictable")
{
"Instruction cache miss" = 0,
"Instruction cache cannot deliver" = 1,
"Stall due to a data dependency" = 2,
"Instruction microTLB miss" = 3,
"Data microTLB miss" = 4,
"Branch instruction executed" = 5,
"Branch mispredicted" = 6,
"Instruction executed" = 7,
"Data cache access" = 10,
"Data cache miss" = 11,
"Data cache write-back" = 12,
"Software changed the PC" = 13,
"Main TLB miss" = 15,
"External memory request" = 16,
"Stall due to LSU being full" = 17,
"Write buffer drained" = 18
}

TYPEDEF ARM1136_PMC(NAME="Performance Monitor Control (ARM1136J)", CLASS="System") COMPOSITE(WIDTH=32)
{
  FIELD[31:28] (NAME="", TYPE=RESERVED(WIDTH=4), ACCESS="0"),
  FIELD[27:12] (NAME="", TYPE=RESERVED(WIDTH=16), ACCESS="V"),
  FIELD[7] (NAME="", TYPE=RESERVED(WIDTH=1), ACCESS="0"),
  SEPARATOR(TEXTNAME="Enable:", GUINAME="Global enable"),
  FIELD[0] (NAME="Global enable", TYPE=FLAG(SET="Y", UNSET="N"), ACCESS="RW"),

  SEPARATOR(TEXTNAME=", Overflow:", GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE"),
  GROUP(NAME="Overflowed")
  {
  SEPARATOR(GUINAME="Clock"),
  FIELD[10] (NAME="Clock overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW"),
  SEPARATOR(GUINAME="Event 0"),
  FIELD[8] (NAME="Event 0 overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW"),
  SEPARATOR(GUINAME="Event 1"),
  FIELD[9] (NAME="Event 1 overflow", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Writing to an overflow bit clears the overflow status"), ACCESS="RW")
  },

  SEPARATOR(TEXTNAME=", Events:", GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE"),
  FIELD[27:20] (NAME="Event 0", TYPE=ARM1136_EventType, ACCESS="RW"),

  SEPARATOR(TEXTNAME=", Events:", GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE"),
  FIELD[19:12] (NAME="Event 1", TYPE=ARM1136_EventType, ACCESS="RW"),

  SEPARATOR(TEXTNAME=", Export:", GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE"),
  FIELD[11] (NAME="Event export", TYPE=FLAG(SET="ENABLED", UNSET="DISABLED"), ACCESS="RW"),

  SEPARATOR(TEXTNAME=", Clocking:", GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE"),
  FIELD[3] (NAME="Clock divisor", TYPE=FLAG(SET="64", UNSET="1"), ACCESS="RW"),

  SEPARATOR(TEXTNAME=", Interrupt:", GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE"),
  GROUP(NAME="Interrupt enable")
  {
  SEPARATOR(GUINAME="Clock"),
  FIELD[6] (NAME="Clock interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW"),
  SEPARATOR(GUINAME="Event 0"),
  FIELD[4] (NAME="Event 0 interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW"),
  SEPARATOR(GUINAME="Event 1"),
  FIELD[5] (NAME="Event 1 interrupt enable", TYPE=FLAG(SET="Y", UNSET="N", TOOLTIP="Generate an interrupt when counter rolls over to zero"), ACCESS="RW")
  },

  SEPARATOR(TEXTNAME=", Reset:", GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE"),
  GROUP(NAME="Reset")
  {
  FIELD[2] (NAME="Reset cycle counter", TYPE=FLAG(SET="reset", UNSET="no action"), ACCESS="RW"), 
  FIELD[1] (NAME="Reset event counters", TYPE=FLAG(SET="reset", UNSET="no action"), ACCESS="RW")
  },
  SEPARATOR(GUINAME="NEWLINE"),
  SEPARATOR(GUINAME=" "),
  SEPARATOR(GUINAME="NEWLINE")
}
  </definition>
</displaytype>

<displaytype>
  <name>FPSID</name>
  <requires></requires>
  <definition>
TYPEDEF tImplementorVFP ENUM(WIDTH=8, DEFAULT="Unknown")
{
  "ARM"   = 0x41,
  "Texas Instruments" = 0x54,
  "Intel" = 0x69
}

TYPEDEF tFormatVFP ENUM(WIDTH=2)
{
  "1" = 0,
  "2" = 1,
  "Reserved" = 2,
  "Non-standard" = 3
}

TYPEDEF tPrecisionVFP ENUM(WIDTH=1)
{
  "Single/Double" = 0,
  "Single only" = 1
}

TYPEDEF tArchVFP ENUM(WIDTH=4, DEFAULT="Unknown")
{
  "VFPv1" = 0,
  "VFPv2" = 1
}


TYPEDEF FPSID(NAME="FPSID", CLASS="System") COMPOSITE(WIDTH=32)
{
  FIELD[31:24] (NAME="Implementor", TYPE=tImplementorVFP, ACCESS="R"),
  SEPARATOR(TEXTNAME=" "), 
  FIELD[19:16] (NAME="Arch", TYPE=tArchVFP, ACCESS="R"),
  SEPARATOR(TEXTNAME=" "),
  FIELD[20] (NAME="Precision", TYPE=tPrecisionVFP, ACCESS="R"),
  SEPARATOR(TEXTNAME=" part "),
  FIELD[15:8] (NAME="Part", TYPE=NUMERIC(WIDTH=8, DEFAULT="HEX"), ACCESS="R"),
  SEPARATOR(TEXTNAME=" variant "),
  FIELD[7:4] (NAME="Variant", TYPE=NUMERIC(WIDTH=4, DEFAULT="UDEC"), ACCESS="R"),
  SEPARATOR(TEXTNAME=" revision "),
  FIELD[3:0] (NAME="Architecture version", TYPE=NUMERIC(WIDTH=4, DEFAULT="UDEC"), ACCESS="R"),
  SEPARATOR(TEXTNAME=" "),
  FIELD[23] (NAME="HWSW", TYPE=FLAG(SET="SW", UNSET="HW"), ACCESS="R"),
  SEPARATOR(TEXTNAME=" format "), 
  FIELD[22:21] (NAME="FMT", TYPE=tFormatVFP, ACCESS="R"),
  SEPARATOR(TEXTNAME=" ")
}
  </definition>
</displaytype>

<displaytype>
  <name>FPEXC</name>
  <requires></requires>
  <definition>
TYPEDEF FPEXC(NAME="FPEXC", CLASS="System") COMPOSITE(WIDTH=32)
{
  FIELD[31] (NAME="EX", TYPE=FLAG(SET="EX", UNSET="ex")),
  SEPARATOR(TEXTNAME=" "),
  FIELD[30] (NAME="Global enable", TYPE=FLAG(SET="EN", UNSET="en")),
  SEPARATOR(TEXTNAME=" "),
  FIELD[29:0] (NAME="Implementation defined", TYPE=NUMERIC(WIDTH=30, DEFAULT="HEX"))
}
  </definition>
</displaytype>

<!-- Debug comms channel -->

<module>
  <type>DCC_CP14</type>
  <register>
     <name>Control</name>
     <bank>Debug Comms Channel</bank>
     <description>Debug Comms Channel Control Register</description>
     <cpreg cp="14" crn="0" crm="0" opcode_2="0"></cpreg>
     <access>RO</access>
     <width>32</width>
     <display>DCC_Control</display>
  </register>
  <register>
     <name>Read</name>
     <bank>Debug Comms Channel</bank>
     <description>Debug Comms Channel Read Register</description>
     <cpreg cp="14" crn="1" crm="0" opcode_2="0"></cpreg>
     <access>RO</access>
     <width>32</width>
  </register>
  <register>
     <name>Write</name>
     <bank>Debug Comms Channel</bank>
     <description>Debug Comms Channel Write Register</description>
     <cpreg cp="14" crn="1" crm="0" opcode_2="0"></cpreg>
     <access>WO</access>
     <width>32</width>
  </register>
</module>

<peripheral>
  <name>DCC_CP14</name>
  <component>
    <name>DCC</name>
    <type>DCC_CP14</type>
  </component>
</peripheral>

<!-- FPA and FPE -->

<module>
  <type>FPA</type>
  <rvoption>FPA</rvoption>
  <register>
     <name>FPCR</name>
     <bank>FPA</bank>
     <cpreg cp="1" opcode_1="2" crn="0" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <dwarf>25</dwarf>
  </register>
  <register>
     <name>FPSR</name>
     <bank>FPA</bank>
     <cpreg cp="1" opcode_1="1" crn="0" crm="0" opcode_2="0"></cpreg>
     <access>RW</access>
     <width>32</width>
     <dwarf>24</dwarf>
  </register>
  <register>
     <name>F0</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="8"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>16</dwarf>
  </register>
  <register>
     <name>F1</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="9"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>17</dwarf>
  </register>
  <register>
     <name>F2</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="10"></cpmem>
     <access>RW</access>
     <width>96</width>
     <display>fp_sci_80</display>
     <dwarf>18</dwarf>
  </register>
  <register>
     <name>F3</name>
     <bank>FPA</bank>
     <cpmem cp="2" p="1" u="1" n="0" w="0" crd="11"></cpmem>
     <access>RW</access>