timedevider.vhd

来自「分频器 FPGＡ程序设计 二分频」· VHDL 代码 · 共 34 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity timedevider is
	port(inclk:in std_logic;
	     outclk: out std_logic;
	     clear:in std_logic);
end timedevider;

architecture behav of timedevider is
--signal clock:std_logic;
signal temp:std_logic_vector(5 downto 0);
begin
   process(inclk,clear)
	begin
		if clear='1' then 
			outclk<='0';
	        temp<="000000";	
		elsif(inclk'event and inclk='1') then
			temp<=temp+'1';
			if temp="011111" then
			   outclk<='1';
			elsif temp="111111" then
			 temp<="000000";
			 outclk<='0';
			end if;
		end if;
	end process;

end behav;