timedevider.fit.summary

来自「分频器 FPGＡ程序设计 二分频」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Wed Sep 06 15:29:46 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : timedevider
Top-level Entity Name : timedevider
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 8 / 5,980 ( < 1 % )
Total pins : 3 / 185 ( 2 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )