prescale_counter.npl

来自「FPGA-CPLD_DesignTool(example5-6）」· NPL 代码 · 共 20 行

JDF F
// Created by Project Navigator ver 1.0
PROJECT prescale_counter
DESIGN prescale_counter Normal
DEVFAM virtexe
DEVFAMTIME 0
DEVICE xcv100e
DEVICETIME 0
DEVPKG bg352
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
FLOW XST Verilog
FLOWTIME 0
MODULE prescale_counter.v
MODSTYLE prescale_counter Normal
DEPASSOC prescale_counter prescale_counter.ucf SYSTEM
[STRATEGY-LIST]
Normal=True