prescale_counter.ucf

来自「FPGA-CPLD_DesignTool(example5-6）」· UCF 代码 · 共 9 行

NET "clk" TNM_NET="clk";
TIMESPEC "TS_clk"=PERIOD "clk" 5ns;
INST "counter_0" TNM="lower_counter";
INST "counter_1" TNM="lower_counter";
TIMEGRP "upper_counter"=FFS(*) EXCEPT "lower_counter";
TIMESPEC "TS_upper_counter"=FROM "upper_counter" TO "upper_counter" TS_clk*4;
OFFSET=OUT 10ns AFTER "clk";
INST "reset" LOC=L26;